| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1200 void fmaxnmv(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64.h | 272 V(fmaxnmv, Fmaxnmv) \
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| H A D | assembler-arm64.cc | 2044 V(fmaxnmv, NEON_FMAXNMV, vd.Is1S()) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2172 LogicVRegister fmaxnmv(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4622 fmaxnmv(vf, rd, rn);
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| H A D | simulator-logic-arm64.cc | 3655 LogicVRegister Simulator::fmaxnmv(VectorFormat vform, LogicVRegister dst, in fmaxnmv() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 3052 void fmaxnmv(const VRegister& vd, const VRegister& vn);
4305 void fmaxnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
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| H A D | simulator-aarch64.cc | 7887 fmaxnmv(vf, rd, rn); in Simulator()
7907 fmaxnmv(vf, rd, rn); in Simulator()
10532 fn = &Simulator::fmaxnmv; in Simulator()
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| H A D | simulator-aarch64.h | 4814 LogicVRegister fmaxnmv(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3018 V(fmaxnmv, Fmaxnmv) \
4595 fmaxnmv(vd, pg, zn); in Fmaxnmv()
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| H A D | assembler-aarch64.cc | 5390 V(fmaxnmv, NEON_FMAXNMV, NEON_FMAXNMV_H) \
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| H A D | assembler-sve-aarch64.cc | 1341 void Assembler::fmaxnmv(const VRegister& vd, in fmaxnmv() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 5669 LogicVRegister Simulator::fmaxnmv(VectorFormat vform,
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| /third_party/vixl/test/aarch64/ |
| H A D | test-cpu-features-aarch64.cc | 3251 TEST_FP_NEON(fmaxnmv_0, fmaxnmv(s0, v1.V4S()))
3658 TEST_FP_NEON_NEONHALF(fmaxnmv_0, fmaxnmv(h0, v1.V4H()))
3659 TEST_FP_NEON_NEONHALF(fmaxnmv_1, fmaxnmv(h0, v1.V8H()))
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| H A D | test-simulator-aarch64.cc | 4955 DEFINE_TEST_NEON_ACROSS_FP(fmaxnmv, Basic)
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| H A D | test-disasm-sve-aarch64.cc | 1545 COMPARE(fmaxnmv(h28, p1, z0.VnH()), "fmaxnmv h28, p1, z0.h"); in TEST()
1546 COMPARE(fmaxnmv(s28, p1, z0.VnS()), "fmaxnmv s28, p1, z0.s"); in TEST()
1547 COMPARE(fmaxnmv(d28, p1, z0.VnD()), "fmaxnmv d28, p1, z0.d"); in TEST()
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| H A D | test-trace-aarch64.cc | 2634 __ fmaxnmv(s27, v19.V4S()); in GenerateTestSequenceNEONFP()
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