Home
last modified time | relevance | path

Searched refs:flush_bits (Results 1 - 25 of 26) sorted by relevance

12

/third_party/mesa3d/src/amd/vulkan/
H A Dsi_cmd_buffer.c906 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH; in si_get_ia_multi_vgt_param()
1053 enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, in gfx10_cs_emit_cache_flush()
1060 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC))); in gfx10_cs_emit_cache_flush()
1062 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE) { in gfx10_cs_emit_cache_flush()
1067 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) { in gfx10_cs_emit_cache_flush()
1075 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) { in gfx10_cs_emit_cache_flush()
1080 if (flush_bits & RADV_CMD_FLAG_INV_L2) { in gfx10_cs_emit_cache_flush()
1085 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) { in gfx10_cs_emit_cache_flush()
1092 } else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA) { in gfx10_cs_emit_cache_flush()
1096 if (flush_bits in gfx10_cs_emit_cache_flush()
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) gfx10_cs_emit_cache_flush() argument
1232 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) si_cs_emit_cache_flush() argument
[all...]
H A Dradv_meta_clear.c867 uint32_t clear_word, flush_bits; in radv_fast_clear_depth() local
877 cmd_buffer->state.flush_bits |= bits & ~*pre_flush; in radv_fast_clear_depth()
878 *pre_flush |= cmd_buffer->state.flush_bits; in radv_fast_clear_depth()
889 flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word); in radv_fast_clear_depth()
898 cmd_buffer->state.flush_bits |= flush_bits; in radv_fast_clear_depth()
903 *post_flush |= flush_bits; in radv_fast_clear_depth()
1303 uint32_t flush_bits = 0; in radv_clear_dcc() local
1341 flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, in radv_clear_dcc()
1346 return flush_bits; in radv_clear_dcc()
1467 uint32_t flush_bits = 0; radv_clear_htile() local
1791 uint32_t clear_color[2], flush_bits = 0; radv_fast_clear_color() local
2297 enum radv_cmd_flush_bits flush_bits = 0; radv_cmd_clear_image() local
[all...]
H A Dradv_meta_fmask_expand.c109 cmd_buffer->state.flush_bits |= radv_dst_access_flush( in radv_expand_fmask_image_inplace()
161 cmd_buffer->state.flush_bits |= in radv_expand_fmask_image_inplace()
166 cmd_buffer->state.flush_bits |= radv_init_fmask(cmd_buffer, image, subresourceRange); in radv_expand_fmask_image_inplace()
H A Dradv_cmd_buffer.c701 cmd_buffer->ace_internal.flush_bits |= in radv_ace_internal_barrier()
702 cmd_buffer->state.flush_bits & RADV_CMD_FLUSH_ALL_COMPUTE & ~RADV_CMD_FLAG_CS_PARTIAL_FLUSH; in radv_ace_internal_barrier()
708 cmd_buffer->ace_internal.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; in radv_ace_internal_barrier()
728 const uint32_t flush_bits = cmd_buffer->ace_internal.flush_bits; in radv_ace_internal_cache_flush() local
732 true, flush_bits, &sqtt_flush_bits, 0); in radv_ace_internal_cache_flush()
734 cmd_buffer->ace_internal.flush_bits = 0; in radv_ace_internal_cache_flush()
2693 cmd_buffer->state.flush_bits |= in radv_emit_fb_mip_change_flush()
2718 cmd_buffer->state.flush_bits |= in radv_emit_mip_change_flush_default()
4270 cmd_buffer->state.flush_bits | in radv_stage_flush()
4335 enum radv_cmd_flush_bits flush_bits = 0; radv_src_access_flush() local
4411 enum radv_cmd_flush_bits flush_bits = 0; radv_dst_access_flush() local
9326 uint32_t flush_bits = 0; radv_init_dcc() local
9374 uint32_t flush_bits = 0; radv_init_color_image_metadata() local
[all...]
H A Dradv_meta_buffer.c253 uint32_t flush_bits = 0; in radv_fill_buffer() local
262 cmd_buffer->state.flush_bits |= in radv_fill_buffer()
267 flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | in radv_fill_buffer()
272 return flush_bits; in radv_fill_buffer()
H A Dradv_meta_fast_clear.c526 cmd_buffer->state.flush_bits |= in radv_process_color_image_layer()
532 cmd_buffer->state.flush_bits |= in radv_process_color_image_layer()
637 cmd_buffer->state.flush_bits |= in radv_process_color_image()
722 cmd_buffer->state.flush_bits |= in radv_decompress_dcc_compute()
821 cmd_buffer->state.flush_bits |= in radv_decompress_dcc_compute()
826 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff); in radv_decompress_dcc_compute()
H A Dradv_meta_resolve.c241 cmd_buffer->state.flush_bits |= in emit_resolve()
264 cmd_buffer->state.flush_bits |= in emit_resolve()
416 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff); in radv_meta_resolve_hardware_image()
613 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_img, &range, 0xffffffff); in radv_cmd_buffer_resolve_subpass_hw()
711 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; in radv_cmd_buffer_resolve_subpass()
713 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; in radv_cmd_buffer_resolve_subpass()
H A Dradv_query.c1037 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE; in radv_query_shader()
1040 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER; in radv_query_shader()
1506 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; in radv_CmdCopyQueryPoolResults()
1649 uint32_t flush_bits = 0; in radv_CmdResetQueryPool() local
1655 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; in radv_CmdResetQueryPool()
1657 flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, in radv_CmdResetQueryPool()
1662 flush_bits |= in radv_CmdResetQueryPool()
1668 if (flush_bits) { in radv_CmdResetQueryPool()
1671 cmd_buffer->state.flush_bits |= flush_bits; in radv_CmdResetQueryPool()
[all...]
H A Dradv_meta_copy.c214 cmd_buffer->state.flush_bits |= in radv_CmdCopyBufferToImage2()
542 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE; in copy_image()
554 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value); in copy_image()
575 cmd_buffer->state.flush_bits |= in radv_CmdCopyImage2()
H A Dradv_meta_copy_vrs_htile.c232 cmd_buffer->state.flush_bits |= in radv_copy_vrs_htile()
300 cmd_buffer->state.flush_bits |= in radv_copy_vrs_htile()
H A Dradv_meta_resolve_cs.c754 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE; in radv_meta_resolve_compute_image()
764 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dest_image, &range, 0xffffffff); in radv_meta_resolve_compute_image()
826 cmd_buffer->state.flush_bits |= in radv_cmd_buffer_resolve_subpass_cs()
847 cmd_buffer->state.flush_bits |= in radv_depth_stencil_resolve_subpass_cs()
912 cmd_buffer->state.flush_bits |= in radv_depth_stencil_resolve_subpass_cs()
930 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value); in radv_depth_stencil_resolve_subpass_cs()
H A Dradv_meta_decompress.c538 cmd_buffer->state.flush_bits |= in radv_expand_depth_stencil_compute()
626 cmd_buffer->state.flush_bits |= in radv_expand_depth_stencil_compute()
633 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value); in radv_expand_depth_stencil_compute()
H A Dradv_acceleration_structure.c2043 enum radv_cmd_flush_bits flush_bits = in radv_CmdBuildAccelerationStructuresKHR() local
2075 cmd_buffer->state.flush_bits |= flush_bits; in radv_CmdBuildAccelerationStructuresKHR()
2159 cmd_buffer->state.flush_bits |= flush_bits; in radv_CmdBuildAccelerationStructuresKHR()
2179 cmd_buffer->state.flush_bits |= flush_bits; in radv_CmdBuildAccelerationStructuresKHR()
2221 cmd_buffer->state.flush_bits |= flush_bits; in radv_CmdBuildAccelerationStructuresKHR()
2242 cmd_buffer->state.flush_bits | in radv_CmdBuildAccelerationStructuresKHR()
[all...]
H A Dradv_meta_dcc_retile.c192 state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image) | in radv_retile_dcc()
284 state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | in radv_retile_dcc()
H A Dradv_meta.c42 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS; in radv_suspend_queries()
43 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS; in radv_suspend_queries()
69 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS; in radv_resume_queries()
70 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS; in radv_resume_queries()
H A Dradv_meta_resolve_fs.c665 cmd_buffer->state.flush_bits |= in emit_resolve()
696 cmd_buffer->state.flush_bits |= in emit_resolve()
H A Dradv_private.h1469 enum radv_cmd_flush_bits flush_bits;
1636 enum radv_cmd_flush_bits flush_bits;
1692 enum radv_cmd_flush_bits flush_bits,
H A Dradv_device.c4598 enum radv_cmd_flush_bits flush_bits = RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE | in radv_update_preamble_cs() local
4604 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; in radv_update_preamble_cs()
4606 flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; in radv_update_preamble_cs()
4609 si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); in radv_update_preamble_cs()
H A Dradv_device_generated_commands.c1383 cmd_buffer->state.flush_bits |= in radv_prepare_dgc()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_pipe_control.c195 const uint32_t flush_bits[NUM_IRIS_DOMAINS] = { in iris_emit_buffer_barrier_for() local
251 bits |= flush_bits[i]; in iris_emit_buffer_barrier_for()
257 bits |= flush_bits[i] | l3_flush_bits[i]; in iris_emit_buffer_barrier_for()
281 bits |= flush_bits[i]; in iris_emit_buffer_barrier_for()
312 bits |= flush_bits[i]; in iris_emit_buffer_barrier_for()
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c60 cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE; in tu6_lazy_emit_tessfactor_addr()
112 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits); in tu_emit_cache_flush()
113 cmd_buffer->state.cache.flush_bits = 0; in tu_emit_cache_flush()
122 if (!cmd_buffer->state.renderpass_cache.flush_bits && in tu_emit_cache_flush_renderpass()
125 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits); in tu_emit_cache_flush_renderpass()
126 cmd_buffer->state.renderpass_cache.flush_bits = 0; in tu_emit_cache_flush_renderpass()
139 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits; in tu_emit_cache_flush_ccu()
142 /* It's unsafe to flush inside condition because we clear flush_bits */ in tu_emit_cache_flush_ccu()
170 cmd_buffer->state.cache.flush_bits = 0; in tu_emit_cache_flush_ccu()
1759 cache->flush_bits in tu_cache_init()
2979 enum tu_cmd_flush_bits flush_bits = 0; tu_flush_for_access() local
[all...]
H A Dtu_cmd_buffer.h246 enum tu_cmd_flush_bits flush_bits; member
/third_party/skia/third_party/externals/libjpeg-turbo/
H A Djchuff.c496 flush_bits(working_state *state) in LOCAL()
664 if (!flush_bits(state)) in LOCAL()
762 /* Load up working state ... flush_bits needs it */ in finish_pass_huff()
770 if (!flush_bits(&state)) in finish_pass_huff()
H A Djcphuff.c374 flush_bits(phuff_entropy_ptr entropy) in flush_bits() function
458 flush_bits(entropy); in emit_restart()
1034 flush_bits(entropy); in finish_pass_phuff()
/third_party/skia/third_party/externals/dng_sdk/source/
H A Ddng_lossless_jpeg.cpp469 void flush_bits (int32 nbits);
1561 inline void dng_lossless_decoder::flush_bits (int32 nbits) in flush_bits() function in dng_lossless_decoder
1628 flush_bits (htbl->numbits [code]); in HuffDecode()
1637 flush_bits (8); in HuffDecode()

Completed in 59 milliseconds

12