| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 2625 LogicVRegister Simulator::fcmla(VectorFormat vform,
2686 LogicVRegister Simulator::fcmla(VectorFormat vform,
2693 fcmla<SimFloat16>(vform, dst, src1, src2, acc, -1, rot);
2695 fcmla<float>(vform, dst, src1, src2, acc, -1, rot);
2697 fcmla<double>(vform, dst, src1, src2, acc, -1, rot);
2703 LogicVRegister Simulator::fcmla(VectorFormat vform,
2712 fcmla<float>(vform, dst, src1, src2, dst, index, rot);
2714 fcmla<double>(vform, dst, src1, src2, dst, index, rot);
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| H A D | macro-assembler-sve-aarch64.cc | 2136 fcmla(ztmp, pg, zn, zm, rot); in Fcmla()
2141 fcmla(zd, pg, zn, zm, rot); in Fcmla()
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| H A D | simulator-aarch64.h | 3712 LogicVRegister fcmla(VectorFormat vform,
3719 LogicVRegister fcmla(VectorFormat vform,
3725 LogicVRegister fcmla(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3619 void fcmla(const VRegister& vd,
3626 void fcmla(const VRegister& vd,
4187 void fcmla(const ZRegister& zda,
4194 void fcmla(const ZRegister& zda,
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| H A D | macro-assembler-aarch64.h | 3324 fcmla(vd, vn, vm, vm_index, rot); in Fcmla()
3332 fcmla(vd, vn, vm, rot); in Fcmla()
4443 fcmla(zda, zn, zm, index, rot); in Fcmla()
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| H A D | simulator-aarch64.cc | 7672 fcmla(vf, rd, rn, rm, rd, rot); in Simulator()
8089 fcmla(vform, rd, rn, rm, index, instr->GetImmRotFcmlaSca()); in Simulator()
10468 fcmla(vform, result, zn, zm, zda, rot); in Simulator()
10506 fcmla(vform, zda, zn, temp, zda, rot); in Simulator()
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| H A D | assembler-aarch64.cc | 4469 void Assembler::fcmla(const VRegister& vd,
4486 void Assembler::fcmla(const VRegister& vd,
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| H A D | assembler-sve-aarch64.cc | 1289 void Assembler::fcmla(const ZRegister& zda, in fcmla() function in vixl::aarch64::Assembler
1310 void Assembler::fcmla(const ZRegister& zda, in fcmla() function in vixl::aarch64::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 376 __ fcmla(z5.VnH(), z0.VnH(), z5.VnH(), 2, 180); in TEST()
379 __ fcmla(z10.VnS(), z8.VnS(), z10.VnS(), 1, 270); in TEST()
382 __ fcmla(z12.VnH(), z12.VnH(), z3.VnH(), 2, 180); in TEST()
385 __ fcmla(z8.VnS(), z8.VnS(), z1.VnS(), 1, 270); in TEST()
1293 __ fcmla(z10.VnH(), z22.VnH(), z3.VnH(), 2, 180); in TEST()
1296 __ fcmla(z12.VnS(), z3.VnS(), z10.VnS(), 1, 270); in TEST()
1742 __ fcmla(z21.VnH(), z31.VnH(), z6.VnH(), 2, 180); in TEST()
1745 __ fcmla(z16.VnS(), z11.VnS(), z6.VnS(), 1, 270); in TEST()
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| H A D | test-cpu-features-aarch64.cc | 3537 TEST_FP_FCMA_NEON(fcmla_0, fcmla(v0.V4S(), v1.V4S(), v2.S(), 0, 180))
3538 TEST_FP_FCMA_NEON(fcmla_1, fcmla(v0.V2S(), v1.V2S(), v2.V2S(), 90))
3539 TEST_FP_FCMA_NEON(fcmla_2, fcmla(v0.V4S(), v1.V4S(), v2.V4S(), 90))
3540 TEST_FP_FCMA_NEON(fcmla_3, fcmla(v0.V2D(), v1.V2D(), v2.V2D(), 90))
3776 TEST_FP_FCMA_NEON_NEONHALF(fcmla_0, fcmla(v0.V4H(), v1.V4H(), v2.H(), 0, 0))
3777 TEST_FP_FCMA_NEON_NEONHALF(fcmla_1, fcmla(v0.V8H(), v1.V8H(), v2.H(), 2, 180))
3778 TEST_FP_FCMA_NEON_NEONHALF(fcmla_2, fcmla(v0.V4H(), v1.V4H(), v2.V4H(), 180))
3779 TEST_FP_FCMA_NEON_NEONHALF(fcmla_3, fcmla(v0.V8H(), v1.V8H(), v2.V8H(), 0))
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| H A D | test-disasm-sve-aarch64.cc | 1432 "fcmla z19.h, p7/m, z16.h, z0.h, #90"); in TEST()
1439 "fcmla z19.s, p7/m, z16.s, z0.s, #90"); in TEST()
1446 "fcmla z19.d, p7/m, z16.d, z0.d, #90"); in TEST()
1454 "fcmla z20.d, p6/m, z15.d, z1.d, #0"); in TEST()
1461 "fcmla z20.d, p6/m, z15.d, z1.d, #180"); in TEST()
1468 "fcmla z20.d, p6/m, z15.d, z1.d, #270"); in TEST()
1476 "fcmla z20.d, p6/m, z15.d, z20.d, #270"); in TEST()
1484 "fcmla z20.d, p6/m, z15.d, z1.d, #270"); in TEST()
1492 "fcmla z31.d, p6/m, z20.d, z1.d, #270\n" in TEST()
1501 "fcmla z3 in TEST()
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