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Searched refs:exp16 (Results 1 - 4 of 4) sorted by relevance

/third_party/vk-gl-cts/framework/delibs/debase/
H A DdeFloat16.c220 int exp16; /* exp16: biased exponent for 16-bit floats */ in deFloat32To16Round() local
229 exp16 = (int) (exp32) - 127 + 15; /* 15/127: exponent bias for 16-bit/32-bit floats */ in deFloat32To16Round()
256 * * If exp16 is less than 0, we are experiencing underflow for the exponent. To encode this underflowed exponent, in deFloat32To16Round()
258 * The real exponent is exp16 - 15. A denormalized 16-bit float can represent -14 via its exponent. in deFloat32To16Round()
260 * So, we just need to right shift the mantissa -exp16 bits. in deFloat32To16Round()
261 * * If exp16 is 0, mantissa shifting requirement is similar to the above. in deFloat32To16Round()
262 * * If exp16 is greater than 30 (0b11110), we are experiencing overflow for the exponent of 16-bit normalized floats. in deFloat32To16Round()
265 else if (exp16 < -10) in deFloat32To16Round()
272 else if (exp16 < in deFloat32To16Round()
377 int exp16; /* exp16: biased exponent for 16-bit floats */ deFloat64To16Round() local
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/third_party/ffmpeg/tests/
H A Dtiny_psnr.c62 static unsigned int exp16(unsigned int a){
/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
H A DShaderCore.cpp567 auto exp16 = halfBits & SIMD::UInt(0x7C00); in halfToFloatBits() local
569 auto isDnormOrZero = CmpEQ(exp16, SIMD::UInt(0)); in halfToFloatBits()
570 auto isInfOrNaN = CmpEQ(exp16, SIMD::UInt(0x7C00)); in halfToFloatBits()
574 auto exp32 = (exp16 + SIMD::UInt(0x1C000)) << 13; in halfToFloatBits()
/third_party/mesa3d/src/broadcom/compiler/
H A Dnir_to_vir.c1335 struct qreg exp16 = vir_ADD(c, exp32, vir_uniform_ui(c, -127 + 15)); in f2f16_rtz() local
1337 /* if (exp16 > 30) */ in f2f16_rtz()
1338 inst = vir_MIN_dest(c, vir_nop_reg(), exp16, vir_uniform_ui(c, 30)); in f2f16_rtz()
1343 /* if (exp16 <= 30) */ in f2f16_rtz()
1346 vir_SHL(c, exp16, vir_uniform_ui(c, 10))), in f2f16_rtz()
1350 /* if (exp16 <= 0) */ in f2f16_rtz()
1351 inst = vir_MIN_dest(c, vir_nop_reg(), exp16, vir_uniform_ui(c, 0)); in f2f16_rtz()
1355 tmp = vir_SHR(c, tmp, vir_SUB(c, vir_uniform_ui(c, 14), exp16)); in f2f16_rtz()
1363 * exp16 < - 10 || exp32 == 0 || exp32 == 0xff in f2f16_rtz()
1367 * !((exp16 > in f2f16_rtz()
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