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Searched refs:drmCommandWriteRead (Results 1 - 25 of 42) sorted by relevance

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/third_party/mesa3d/src/gallium/winsys/svga/drm/
H A Dvmw_screen_ioctl.c111 ret = drmCommandWriteRead(vws->ioctl.drm_fd, in vmw_ioctl_extended_context_create()
187 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE, in vmw_ioctl_surface_create()
273 ret = drmCommandWriteRead(vws->ioctl.drm_fd, in vmw_ioctl_gb_surface_create()
312 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE, in vmw_ioctl_gb_surface_create()
435 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF_EXT, in vmw_ioctl_gb_surface_ref()
463 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF, in vmw_ioctl_gb_surface_ref()
629 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg, in vmw_ioctl_region_create()
827 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_SIGNALED, in vmw_ioctl_fence_signalled()
856 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT, in vmw_ioctl_fence_finish()
892 ret = drmCommandWriteRead(vw in vmw_ioctl_shader_create()
[all...]
/third_party/libdrm/freedreno/msm/
H A Dmsm_bo.c44 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, in bo_allocate()
100 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_MADVISE, &req, sizeof(req)); in msm_bo_madvise()
114 drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); in msm_bo_iova()
145 ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_NEW, in msm_bo_new_handle()
H A Dmsm_pipe.c41 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_GET_PARAM, in query_param()
117 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_NEW, in open_submitqueue()
/third_party/libdrm/radeon/
H A Dradeon_bo_gem.c105 r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE, in bo_open()
164 r = drmCommandWriteRead(boi->bom->fd, in bo_map()
220 ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY, in bo_is_busy()
237 r = drmCommandWriteRead(boi->bom->fd, in bo_set_tiling()
252 r = drmCommandWriteRead(boi->bom->fd, in bo_get_tiling()
349 r = drmCommandWriteRead(boi->bom->fd, in radeon_gem_set_domain()
/third_party/mesa3d/src/freedreno/drm/msm/
H A Dmsm_bo.c45 drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); in bo_allocate()
105 drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_MADVISE, &req, sizeof(req)); in msm_bo_madvise()
121 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); in msm_bo_iova()
186 ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_NEW, &req, sizeof(req)); in new_handle()
H A Dmsm_pipe.c43 drmCommandWriteRead(pipe->dev->fd, DRM_MSM_GET_PARAM, &req, sizeof(req)); in query_param()
64 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_QUERY, &req, in query_queue_param()
119 return drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SET_PARAM, in set_param()
174 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_NEW, &req, in open_submitqueue()
H A Dmsm_device.c82 if (!drmCommandWriteRead(fd, DRM_MSM_GEM_NEW, in msm_device_new()
/third_party/libdrm/amdgpu/
H A Damdgpu_bo.c86 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE, in amdgpu_bo_alloc()
121 return drmCommandWriteRead(bo->dev->fd, in amdgpu_bo_set_metadata()
142 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_METADATA, in amdgpu_bo_query_info()
156 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_OP, in amdgpu_bo_query_info()
450 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_MMAP, &args, in amdgpu_bo_cpu_map()
518 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_WAIT_IDLE, in amdgpu_bo_wait_for_idle()
584 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR, in amdgpu_create_bo_from_user_mem()
614 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, in amdgpu_bo_list_create_raw()
630 return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, in amdgpu_bo_list_destroy_raw()
676 r = drmCommandWriteRead(de in amdgpu_bo_list_create()
[all...]
H A Damdgpu_vm.c36 return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, in amdgpu_vm_reserve_vmid()
48 return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, in amdgpu_vm_unreserve_vmid()
H A Damdgpu_cs.c78 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args)); in amdgpu_cs_ctx_create2()
126 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, in amdgpu_cs_ctx_free()
185 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, in amdgpu_cs_ctx_stable_pstate()
204 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, in amdgpu_cs_query_reset_state()
225 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, in amdgpu_cs_query_reset_state2()
898 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS, in amdgpu_cs_submit_raw()
927 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS, in amdgpu_cs_submit_raw2()
967 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE, in amdgpu_cs_fence_to_handle()
/third_party/libdrm/tests/radeon/
H A Drbo.c72 r = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE, in rbo()
108 r = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_MMAP, in rbo_map()
167 ret = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_WAIT_IDLE, in rbo_wait()
/third_party/libdrm/freedreno/kgsl/
H A Dkgsl_bo.c57 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_ALLOC, in bo_alloc()
144 ret = drmCommandWriteRead(dev->fd, DRM_KGSL_GEM_CREATE, in kgsl_bo_new_handle()
237 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO, in kgsl_bo_gpuaddr()
301 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO, in kgsl_bo_get_timestamp()
/third_party/libdrm/nouveau/
H A Dabi16.c45 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, in abi16_chan_nv04()
66 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, in abi16_chan_nvc0()
92 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, in abi16_chan_nve0()
158 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, in abi16_ntfy()
354 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_NEW, in abi16_bo_init()
/third_party/libdrm/etnaviv/
H A Detnaviv_perfmon.c42 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_SIG, &req, sizeof(req)); in etna_perfmon_query_signals()
74 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_DOM, &req, sizeof(req)); in etna_perfmon_query_domains()
H A Detnaviv_bo.c112 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GEM_NEW, in etna_bo_new()
140 ret = drmCommandWriteRead(bo->dev->fd, DRM_ETNAVIV_GEM_INFO, in get_buffer_info()
H A Detnaviv_gpu.c38 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GET_PARAM, &req, sizeof(req)); in get_param()
/third_party/mesa3d/src/etnaviv/drm/
H A Detnaviv_perfmon.c42 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_SIG, &req, sizeof(req)); in etna_perfmon_query_signals()
74 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_DOM, &req, sizeof(req)); in etna_perfmon_query_domains()
H A Detnaviv_bo.c200 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GEM_NEW, in etna_bo_new()
396 ret = drmCommandWriteRead(bo->dev->fd, DRM_ETNAVIV_GEM_INFO, in etna_bo_map()
H A Detnaviv_gpu.c38 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GET_PARAM, &req, sizeof(req)); in get_param()
H A Detnaviv_device.c71 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GET_PARAM, &req, sizeof(req)); in etna_device_new()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_bo.c67 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, in radeon_real_bo_is_busy()
186 if (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_OP, in radeon_bo_get_initial_domain()
383 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, in radeon_bo_destroy()
459 if (drmCommandWriteRead(bo->rws->fd, in radeon_bo_do_map()
651 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, in radeon_create_bo()
705 r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va)); in radeon_create_bo()
887 drmCommandWriteRead(bo->rws->fd, in radeon_bo_get_metadata()
996 drmCommandWriteRead(bo->rws->fd, in radeon_bo_set_metadata()
1113 if (drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR, in radeon_winsys_bo_from_ptr()
1153 r = drmCommandWriteRead(w in radeon_winsys_bo_from_ptr()
[all...]
H A Dradeon_drm_winsys.c83 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO, in radeon_set_fd_access()
115 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)); in radeon_get_drm_value()
346 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR, in do_winsys_init()
351 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, in do_winsys_init()
/third_party/libdrm/omap/
H A Domap_drm.c139 ret = drmCommandWriteRead(dev->fd, DRM_OMAP_GET_PARAM, &req, sizeof(req)); in omap_get_param()
203 if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) { in omap_bo_new_impl()
267 int ret = drmCommandWriteRead(bo->dev->fd, DRM_OMAP_GEM_INFO, in get_buffer_info()
/third_party/libdrm/tegra/
H A Dtegra.c139 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_CREATE, &args, in drm_tegra_bo_new()
208 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_MMAP, &args, in drm_tegra_bo_map()
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_drm.c72 int ret = drmCommandWriteRead(dev->local_fd, DRM_MSM_GET_PARAM, &req, in tu_drm_get_param()
155 int ret = drmCommandWriteRead(dev->fd, in tu_drm_submitqueue_new()
190 int ret = drmCommandWriteRead(dev->fd, in tu_gem_info()
266 int ret = drmCommandWriteRead(dev->fd, in tu_bo_init_new()
1031 int ret = drmCommandWriteRead(queue->device->fd, in tu_queue_submit_locked()

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