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Searched refs:dl (Results 1 - 25 of 600) sorted by relevance

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/third_party/ffmpeg/libavcodec/
H A Dttadsp.c23 static void tta_filter_process_c(int32_t *qmi, int32_t *dx, int32_t *dl, in tta_filter_process_c() argument
36 round += dl[0] * qm[0] + dl[1] * qm[1] + dl[2] * qm[2] + dl[3] * qm[3] + in tta_filter_process_c()
37 dl[4] * qm[4] + dl[5] * qm[5] + dl[6] * qm[6] + dl[7] * qm[7]; in tta_filter_process_c()
40 dl[ in tta_filter_process_c()
[all...]
H A Dttaencdsp.c23 static void ttaenc_filter_process_c(int32_t *qm, int32_t *dx, int32_t *dl, in ttaenc_filter_process_c() argument
34 round += dl[0] * qm[0] + dl[1] * qm[1] + dl[2] * qm[2] + dl[3] * qm[3] + in ttaenc_filter_process_c()
35 dl[4] * qm[4] + dl[5] * qm[5] + dl[6] * qm[6] + dl[7] * qm[7]; in ttaenc_filter_process_c()
38 dl[ in ttaenc_filter_process_c()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp209 const SDLoc &dl, SelectionDAG &DAG) const { in getInt()
211 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
259 HexagonTargetLowering::opJoin(const VectorPair &Ops, const SDLoc &dl, in opJoin() argument
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
266 HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl, in opSplit() argument
271 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
297 const SDLoc &dl(ElemIdx); in convertToByteIndex()
298 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
299 {ElemIdx, DAG.getConstant(L, dl, MV in convertToByteIndex()
208 getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops, const SDLoc &dl, SelectionDAG &DAG) const getInt() argument
319 getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1, ArrayRef<int> Mask, SelectionDAG &DAG) const getByteShuffle() argument
350 buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildHvxVectorReg() argument
502 createHvxPrefixPred(SDValue PredV, const SDLoc &dl, unsigned BitBytes, bool ZeroFill, SelectionDAG &DAG) const createHvxPrefixPred() argument
591 buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildHvxVectorPred() argument
664 extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxElementReg() argument
688 extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxElementPred() argument
707 insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxElementReg() argument
752 insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxElementPred() argument
768 extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxSubvectorReg() argument
813 extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxSubvectorPred() argument
877 insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxSubvectorReg() argument
964 insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxSubvectorPred() argument
1009 extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy, bool ZeroExt, SelectionDAG &DAG) const extendHvxVectorPred() argument
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H A DHexagonISelLowering.cpp168 SelectionDAG &DAG, const SDLoc &dl) { in CreateCopyOfByValArgument()
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
170 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), in CreateCopyOfByValArgument()
197 const SDLoc &dl, SelectionDAG &DAG) const { in LowerReturn()
218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
231 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
320 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
344 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
348 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, Pred in LowerCallResult()
166 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) CreateCopyOfByValArgument() argument
193 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const LowerReturn() argument
318 LowerCallResult( SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const LowerCallResult() argument
375 SDLoc &dl = CLI.DL; LowerCall() local
745 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
1736 validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl, unsigned NeedAlign) const validateConstPtrAlignment() argument
2182 buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildVector32() argument
2265 buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildVector64() argument
2326 extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ValTy, MVT ResTy, SelectionDAG &DAG) const extractVector() argument
2425 insertVector(SDValue VecV, SDValue ValV, SDValue IdxV, const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const insertVector() argument
2491 expandPredicate(SDValue Vec32, const SDLoc &dl, SelectionDAG &DAG) const expandPredicate() argument
2500 contractPredicate(SDValue Vec64, const SDLoc &dl, SelectionDAG &DAG) const contractPredicate() argument
2509 getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const getZero() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp167 inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) { in getI16Imm() argument
168 return CurDAG->getTargetConstant(Imm, dl, MVT::i16); in getI16Imm()
173 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { in getI32Imm() argument
174 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm()
179 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) { in getI64Imm() argument
180 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm()
184 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) { in getSmallIPtrImm() argument
186 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout())); in getSmallIPtrImm()
220 const SDLoc &dl);
322 SDLoc dl(O
399 DebugLoc dl; InsertVRSaveCode() local
437 DebugLoc dl; getGlobalBaseReg() local
888 selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) selectI64ImmDirect() argument
973 selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) selectI64Imm() argument
1706 getI32Imm(unsigned Imm, const SDLoc &dl) getI32Imm() argument
1725 ExtendToInt64(SDValue V, const SDLoc &dl) ExtendToInt64() argument
1739 TruncateToInt32(SDValue V, const SDLoc &dl) TruncateToInt32() argument
1753 SelectAndParts32(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) SelectAndParts32() argument
1955 SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt, bool Repl32, unsigned MaskStart, unsigned MaskEnd, unsigned *InstCnt = nullptr) SelectRotMask64() argument
2019 SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl, unsigned RLAmt, bool Repl32, unsigned MaskStart, unsigned MaskEnd, unsigned *InstCnt = nullptr) SelectRotMaskIns64() argument
2067 SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) SelectAndParts64() argument
2832 getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, ZeroCompare CmpTy) getCompoundZeroComparisonInGPR() argument
2906 get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) get32BitZExtCompare() argument
3079 get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) get32BitSExtCompare() argument
3251 get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) get64BitZExtCompare() argument
3408 get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) get64BitSExtCompare() argument
3695 SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl) SelectCC() argument
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H A DPPCISelLowering.cpp132 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
2414 // FIXME dl should come from parent load or store, not from address in SelectAddressRegImm()
2415 SDLoc dl(N); in SelectAddressRegImm()
2424 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
2463 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
2475 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0)); in SelectAddressRegImm()
2488 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
2490 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl, in SelectAddressRegImm()
2493 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); in SelectAddressRegImm()
2498 Disp = DAG.getTargetConstant(0, dl, getPointerT in SelectAddressRegImm()
2732 getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const getTOCEntry() argument
3452 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
3470 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments_32SVR4() argument
3741 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments_64SVR4() argument
4153 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments_Darwin() argument
4827 StoreTailCallArgumentsToStackSlot( SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) StoreTailCallArgumentsToStackSlot() argument
4844 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) EmitTailCallStoreFPAndRetAddr() argument
4925 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) CreateCopyOfByValArgument() argument
4936 LowerMemOpCallTo( SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) LowerMemOpCallTo() argument
4960 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) PrepareTailCall() argument
4997 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerCallResult() argument
5129 transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) transformCallee() argument
5241 prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl) prepareIndirectCall() argument
5252 prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, ImmutableCallSite CS, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) prepareDescriptorIndirectCall() argument
5345 buildCallOperands(SmallVectorImpl<SDValue> &Ops, CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget, bool isIndirect) buildCallOperands() argument
5424 FinishCall( CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const FinishCall() argument
5493 SDLoc &dl = CLI.DL; LowerCall() local
5565 LowerCall_32SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const LowerCall_32SVR4() argument
5818 LowerCall_64SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const LowerCall_64SVR4() argument
6479 LowerCall_Darwin( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const LowerCall_Darwin() argument
6969 truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl) truncateScalarIntegerArg() argument
6985 LowerFormalArguments_AIX( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments_AIX() argument
7061 LowerCall_AIX( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const LowerCall_AIX() argument
7229 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const LowerReturn() argument
7971 widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) widenVec() argument
8451 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) BuildSplatI() argument
8471 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) BuildIntrinsicOp() argument
8480 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) BuildIntrinsicOp() argument
8490 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) BuildIntrinsicOp() argument
8500 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) BuildVSLDOI() argument
8908 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) GeneratePerfectShuffle() argument
10659 DebugLoc dl = MI.getDebugLoc(); EmitAtomicBinary() local
10763 DebugLoc dl = MI.getDebugLoc(); EmitPartwordAtomicBinary() local
11219 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11259 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11327 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11495 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11574 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11753 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11808 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
11830 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp293 SDLoc dl(N); in PromoteIntRes_BITCAST()
301 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
309 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
318 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
333 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
337 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
347 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
355 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
356 DAG.getConstant(ShiftAmt, dl, ShiftAmtT in PromoteIntRes_BITCAST()
3803 IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl) IntegerExpandSetCCOperands() argument
4007 SDLoc dl = SDLoc(N); ExpandIntOp_SETCCCARRY() local
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H A DLegalizeTypesGeneric.cpp45 SDLoc dl(N); in ExpandRes_BITCAST()
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
76 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
77 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
82 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
83 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
90 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoV in ExpandRes_BITCAST()
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H A DLegalizeDAG.cpp124 const SDLoc &dl);
126 const SDLoc &dl);
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
137 bool &NeedInvert, const SDLoc &dl, SDValue &Chain,
162 const SDLoc &dl);
164 const SDLoc &dl, SDValue ChainIn);
177 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
179 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
182 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
183 SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
259 ShuffleWithNarrowerEltType( EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef<int> Mask) const ShuffleWithNarrowerEltType() argument
362 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, const SDLoc &dl) PerformInsertVectorEltInMemory() argument
396 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, const SDLoc &dl) ExpandINSERT_VECTOR_ELT() argument
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H A DTargetLowering.cpp129 const SDLoc &dl, in makeLibCall()
168 CLI.setDebugLoc(dl) in makeLibCall()
286 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands()
289 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, in softenSetCCOperands()
296 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands()
402 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
404 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
418 SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode); in softenSetCCOperands()
419 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
423 NewLHS = DAG.getSetCC(dl, SetCCV in softenSetCCOperands()
126 makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue InChain) const makeLibCall() argument
283 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS) const softenSetCCOperands() argument
293 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling) const softenSetCCOperands() argument
4635 BuildExactSDIV(const TargetLowering &TLI, SDNode *N, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) BuildExactSDIV() argument
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/third_party/ffmpeg/libavcodec/x86/
H A Dttaencdsp.asm34 cglobal ttaenc_filter_process, 5,5,%2, qm, dx, dl, error, in, shift, round
74 ; filter->dl[0] * filter->qm[0] +
75 pshufd m3, m2, 0xe ; filter->dl[1] * filter->qm[1] +
76 paddd m2, m3 ; filter->dl[2] * filter->qm[2] +
77 ; filter->dl[3] * filter->qm[3] +
78 movd m6, roundm ; filter->dl[4] * filter->qm[4] +
79 paddd m6, m2 ; filter->dl[5] * filter->qm[5] +
80 pshufd m2, m2, 0x1 ; filter->dl[6] * filter->qm[6] +
81 paddd m6, m2 ; filter->dl[7] * filter->qm[7];
86 palignr m2, m1, m0, 4 ; filter->dl[
[all...]
H A Dttadsp.asm34 cglobal tta_filter_process, 5,5,%2, qm, dx, dl, error, in, shift, round
74 ; filter->dl[0] * filter->qm[0] +
75 pshufd m3, m2, 0xe ; filter->dl[1] * filter->qm[1] +
76 paddd m2, m3 ; filter->dl[2] * filter->qm[2] +
77 ; filter->dl[3] * filter->qm[3] +
78 movd m6, roundm ; filter->dl[4] * filter->qm[4] +
79 paddd m6, m2 ; filter->dl[5] * filter->qm[5] +
80 pshufd m2, m2, 0x1 ; filter->dl[6] * filter->qm[6] +
81 paddd m6, m2 ; filter->dl[7] * filter->qm[7];
86 palignr m2, m1, m0, 4 ; filter->dl[
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp252 SDLoc dl(GA); in getGlobalAddressWrapper()
255 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
260 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
262 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
326 SDLoc dl(CP); in LowerConstantPool()
336 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
349 SDLoc dl(Op); in LowerBR_JT()
358 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
361 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
362 DAG.getConstant(1, dl, MV in LowerBR_JT()
1034 SDLoc &dl = CLI.DL; LowerCall() local
1061 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) LowerCallResult() argument
1107 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerCCCCallTo() argument
1241 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
1260 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerCCCArguments() argument
1437 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const LowerReturn() argument
1527 DebugLoc dl = MI.getDebugLoc(); EmitInstrWithCustomInserter() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp47 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, in EmitTargetCodeForMemset()
88 CLI.setDebugLoc(dl) in EmitTargetCodeForMemset()
134 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
140 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); in EmitTargetCodeForMemset()
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
149 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
150 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag); in EmitTargetCodeForMemset()
155 Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
158 Chain = DAG.getCopyToReg(Chain, dl, Use64BitReg in EmitTargetCodeForMemset()
46 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
186 emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, MVT AVT) emitRepmovs() argument
208 emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size) emitRepmovsB() argument
236 emitConstantSizeRepmov( SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) emitConstantSizeRepmov() argument
292 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm/crypto/rc4/
H A Drc4-x86_64.s51 addb %dl,%al
55 xorb (%r12),%dl
56 movb %dl,(%r12,%r13,1)
71 addb %al,%dl
79 addb %bl,%dl
87 addb %al,%dl
95 addb %bl,%dl
103 addb %al,%dl
111 addb %bl,%dl
119 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm_avx2/crypto/rc4/
H A Drc4-x86_64.s51 addb %dl,%al
55 xorb (%r12),%dl
56 movb %dl,(%r12,%r13,1)
71 addb %al,%dl
79 addb %bl,%dl
87 addb %al,%dl
95 addb %bl,%dl
103 addb %al,%dl
111 addb %bl,%dl
119 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/BSD-x86_64/asm/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/BSD-x86_64/asm_avx2/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/linux-x86_64/asm/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/linux-x86_64/asm_avx2/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/solaris64-x86_64-gcc/asm/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/node/deps/openssl/config/archs/solaris64-x86_64-gcc/asm_avx2/crypto/rc4/
H A Drc4-x86_64.s54 addb %dl,%al
58 xorb (%r12),%dl
59 movb %dl,(%r12,%r13,1)
74 addb %al,%dl
82 addb %bl,%dl
90 addb %al,%dl
98 addb %bl,%dl
106 addb %al,%dl
114 addb %bl,%dl
122 addb %al,%dl
[all...]
/third_party/pulseaudio/src/pulsecore/
H A Dmodinfo.c41 pa_modinfo *pa_modinfo_get_by_handle(lt_dlhandle dl, const char *module_name) { in pa_modinfo_get_by_handle() argument
46 pa_assert(dl); in pa_modinfo_get_by_handle()
50 if ((func = (const char* (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_AUTHOR))) in pa_modinfo_get_by_handle()
53 if ((func = (const char* (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_DESCRIPTION))) in pa_modinfo_get_by_handle()
56 if ((func = (const char* (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_USAGE))) in pa_modinfo_get_by_handle()
59 if ((func = (const char* (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_VERSION))) in pa_modinfo_get_by_handle()
62 if ((func = (const char* (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_DEPRECATED))) in pa_modinfo_get_by_handle()
65 if ((func2 = (bool (*)(void)) pa_load_sym(dl, module_name, PA_SYMBOL_LOAD_ONCE))) in pa_modinfo_get_by_handle()
72 lt_dlhandle dl; in pa_modinfo_get_by_name() local
77 if (!(dl in pa_modinfo_get_by_name()
[all...]
/third_party/elfutils/libelf/
H A Delf32_updatefile.c310 Elf_Data_List *dl = &scn->data_list; in __elfw2() local
316 assert (dl->data.d.d_off >= 0); in __elfw2()
317 assert ((GElf_Off) dl->data.d.d_off <= shdr->sh_size); in __elfw2()
318 assert (dl->data.d.d_size <= (shdr->sh_size in __elfw2()
319 - (GElf_Off) dl->data.d.d_off)); in __elfw2()
322 if (scn_start + dl->data.d.d_off > last_position in __elfw2()
323 && (dl->data.d.d_off == 0 in __elfw2()
324 || ((scn->flags | dl->flags | elf->flags) in __elfw2()
327 fill_mmap (dl->data.d.d_off, last_position, scn_start, in __elfw2()
331 last_position = scn_start + dl in __elfw2()
713 Elf_Data_List *dl = &scn->data_list; __elfw2() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp40 DebugLoc dl; in emitPrologueInsns() local
51 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
55 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
59 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
63 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
67 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX9) in emitPrologueInsns()
78 DebugLoc dl; in emitEpilogueInsns() local
89 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX11) in emitEpilogueInsns()
92 BuildMI(MBB, MBBI, dl, TII.get(VE::LDSri), VE::SX16) in emitEpilogueInsns()
95 BuildMI(MBB, MBBI, dl, TI in emitEpilogueInsns()
110 DebugLoc dl; emitSPAdjustment() local
140 DebugLoc dl; emitSPExtend() local
186 DebugLoc dl; emitPrologue() local
272 DebugLoc dl = MBBI->getDebugLoc(); emitEpilogue() local
[all...]

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