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Searched refs:ctx_cs (Results 1 - 3 of 3) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_pipeline.c5524 radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_depth_stencil_state() argument
5527 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control); in radv_pipeline_emit_depth_stencil_state()
5529 radeon_set_context_reg_seq(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, 2); in radv_pipeline_emit_depth_stencil_state()
5530 radeon_emit(ctx_cs, ds_state->db_render_override); in radv_pipeline_emit_depth_stencil_state()
5531 radeon_emit(ctx_cs, ds_state->db_render_override2); in radv_pipeline_emit_depth_stencil_state()
5535 radv_pipeline_emit_blend_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_blend_state() argument
5541 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8); in radv_pipeline_emit_blend_state()
5542 radeon_emit_array(ctx_cs, blend->cb_blend_control, 8); in radv_pipeline_emit_blend_state()
5543 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); in radv_pipeline_emit_blend_state()
5547 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OP in radv_pipeline_emit_blend_state()
5557 radv_pipeline_emit_raster_state(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline, const struct radv_graphics_pipeline_info *info) radv_pipeline_emit_raster_state() argument
5591 radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_multisample_state() argument
5619 radv_pipeline_emit_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_vgt_gs_mode() argument
5647 radv_pipeline_emit_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline, const struct radv_shader *shader) radv_pipeline_emit_hw_vs() argument
5759 radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline, const struct radv_shader *shader) radv_pipeline_emit_hw_ngg() argument
5964 radv_pipeline_emit_vertex_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_vertex_shader() argument
5985 radv_pipeline_emit_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_tess_shaders() argument
6014 radv_pipeline_emit_tess_state(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline, const struct radv_graphics_pipeline_info *info) radv_pipeline_emit_tess_state() argument
6094 radv_pipeline_emit_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline, const struct radv_shader *gs) radv_pipeline_emit_hw_gs() argument
6186 radv_pipeline_emit_geometry_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_geometry_shader() argument
6204 radv_pipeline_emit_mesh_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_mesh_shader() argument
6286 radv_pipeline_emit_ps_inputs(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_ps_inputs() argument
6386 radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_fragment_shader() argument
6431 radv_pipeline_emit_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_vgt_vertex_reuse() argument
6450 radv_pipeline_emit_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) radv_pipeline_emit_vgt_shader_config() argument
6524 radv_pipeline_emit_cliprect_rule(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline_info *info) radv_pipeline_emit_cliprect_rule() argument
6554 gfx10_pipeline_emit_ge_cntl(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) gfx10_pipeline_emit_ge_cntl() argument
6586 radv_pipeline_emit_vgt_gs_out(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline, uint32_t vgt_gs_out_prim_type) radv_pipeline_emit_vgt_gs_out() argument
6600 gfx103_pipeline_emit_vgt_draw_payload_cntl(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline, const struct radv_graphics_pipeline_info *info) gfx103_pipeline_emit_vgt_draw_payload_cntl() argument
6638 gfx103_pipeline_emit_vrs_state(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline, const struct radv_graphics_pipeline_info *info) gfx103_pipeline_emit_vrs_state() argument
6691 struct radeon_cmdbuf *ctx_cs = &pipeline->base.ctx_cs; radv_pipeline_emit_pm4() local
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H A Dradv_cmd_buffer.c1587 cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.cdw != pipeline->base.ctx_cs.cdw || in radv_emit_graphics_pipeline()
1589 memcmp(cmd_buffer->state.emitted_graphics_pipeline->base.ctx_cs.buf, pipeline->base.ctx_cs.buf, in radv_emit_graphics_pipeline()
1590 pipeline->base.ctx_cs.cdw * 4)) { in radv_emit_graphics_pipeline()
1591 radeon_emit_array(cmd_buffer->cs, pipeline->base.ctx_cs.buf, pipeline->base.ctx_cs.cdw); in radv_emit_graphics_pipeline()
5495 assert(!pipeline->base.ctx_cs.cdw); in radv_emit_compute_pipeline()
H A Dradv_private.h2120 struct radeon_cmdbuf ctx_cs;

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