| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 2251 COMPARE(csneg(w18, w19, w20, vs), "csneg w18, w19, w20, vs"); in TEST()
2252 COMPARE(csneg(x21, x22, x23, vc), "csneg x21, x22, x23, vc"); in TEST()
2270 COMPARE(csneg(x6, x7, x8, al), "csneg x6, x7, x8, al"); in TEST()
2271 COMPARE(csneg(x7, x8, x9, nv), "csneg x7, x8, x9, nv"); in TEST()
|
| H A D | test-trace-aarch64.cc | 137 __ csneg(w7, w8, w9, hi); in GenerateTestSequenceBase()
138 __ csneg(w7, w8, w9, ls); in GenerateTestSequenceBase()
139 __ csneg(x10, x11, x12, eq); in GenerateTestSequenceBase()
140 __ csneg(x10, x11, x12, ne); in GenerateTestSequenceBase()
|
| H A D | test-cpu-features-aarch64.cc | 260 TEST_NONE(csneg_0, csneg(w0, w1, w2, ge))
261 TEST_NONE(csneg_1, csneg(x0, x1, x2, cc))
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 491 csneg(rd, rn, rm, cond); in Csneg()
|
| H A D | assembler-arm64.h | 700 void csneg(const Register& rd, const Register& rn, const Register& rm,
|
| H A D | assembler-arm64.cc | 1030 void Assembler::csneg(const Register& rd, const Register& rn, in csneg() function in v8::internal::Assembler
1059 csneg(rd, rn, rn, NegateCondition(cond)); in cneg()
|
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 749 void Assembler::csneg(const Register& rd, in csneg() function in vixl::aarch64::Assembler
785 csneg(rd, rn, rn, InvertCondition(cond)); in cneg()
|
| H A D | assembler-aarch64.h | 923 void csneg(const Register& rd,
|
| H A D | macro-assembler-aarch64.h | 1457 csneg(rd, rn, rm, cond); in Csneg()
|