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Searched refs:covers (Results 1 - 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp36 if (!covers(RC)) in verify()
38 // Verify that the register bank covers all the sub classes of the in verify()
39 // classes it covers. in verify()
43 // both agree on the covers. in verify()
51 // all the register classes it covers. in verify()
54 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers() function in RegisterBank
106 if (!covers(RC)) in print()
H A DRegisterBankInfo.cpp127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
141 // Otherwise, all we can do is ensure the bank covers the class, and set it. in constrainGenericRegister()
142 if (RB && !RB->covers(RC)) in constrainGenericRegister()
565 // Check that the union of the partial mappings covers the whole value, in verify()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
165 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
/third_party/mesa3d/src/gallium/drivers/zink/
H A Dzink_blit.c453 zink_blit_region_covers(struct u_rect region, struct u_rect covers) in zink_blit_region_covers() argument
462 MIN2(covers.x0, covers.x1), in zink_blit_region_covers()
463 MAX2(covers.x0, covers.x1), in zink_blit_region_covers()
464 MIN2(covers.y0, covers.y1), in zink_blit_region_covers()
465 MAX2(covers.y0, covers.y1), in zink_blit_region_covers()
H A Dzink_context.h524 zink_blit_region_covers(struct u_rect region, struct u_rect covers);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegisterBank.h67 /// Check whether this register bank covers \p RC.
68 /// In other words, check if this register bank fully covers
71 bool covers(const TargetRegisterClass &RC) const;
87 /// this register bank covers.
/third_party/skia/third_party/externals/harfbuzz/src/
H A Dhb-ot-layout-gdef-table.hh422 bool covers (unsigned int set_index, hb_codepoint_t glyph_id) const in covers() function
470 bool covers (unsigned int set_index, hb_codepoint_t glyph_id) const in covers() function
473 case 1: return u.format1.covers (set_index, glyph_id); in covers()
556 { return version.to_int () >= 0x00010002u && (this+markGlyphSetsDef).covers (set_index, glyph_id); } in mark_set_covers()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64RegisterBankInfo.cpp67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
73 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
75 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
80 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) && in AArch64RegisterBankInfo()
/third_party/ffmpeg/tests/fate/
H A Dcover-art.mak49 # Also covers muxing and demuxing of nonstandard channel layouts into FLAC
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp38 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DLiveInterval.cpp494 bool LiveRange::covers(const LiveRange &Other) const {
1104 assert(covers(SR));
H A DMachineVerifier.cpp2723 if (!LI.covers(SR)) { in verifyLiveInterval()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DLiveInterval.h465 /// [1,5](5,10] covers (3,7].
466 bool covers(const LiveRange &Other) const;
/third_party/libunwind/libunwind/doc/
H A Dlibunwind-dynamic.tex229 negative value indicates that the region covers the last \emph{N}
250 \Prog{libunwind} knows that the region covers the end of the procedure
/third_party/ffmpeg/libswscale/x86/
H A Doutput.asm116 ; the rep here is for the 8-bit output MMX case, where dither covers
/third_party/ffmpeg/libavutil/x86/
H A Dx86inc.asm123 ; covers most of x264's asm.

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