/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | ir3_const.h | 71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts() 131 if (16 * v->constlen <= state->range[i].offset) in ir3_emit_constant_data() 137 size = MIN2(size, (16 * v->constlen) - state->range[i].offset); in ir3_emit_constant_data() 177 if (16 * v->constlen <= state->range[i].offset) in ir3_emit_user_consts() 183 size = MIN2(size, (16 * v->constlen) - state->range[i].offset); in ir3_emit_user_consts() 216 if (v->constlen > offset) { in ir3_emit_ubos() 250 assert(offset * 4 + params <= v->constlen * 4); in ir3_emit_ubos() 264 if (v->constlen > offset) { in ir3_emit_image_dims() 304 uint32_t size = MIN2(ARRAY_SIZE(dims), v->constlen * 4 - offset * 4); in ir3_emit_image_dims() 322 size = MIN2(size + base, v->constlen) in ir3_emit_immediates() [all...] |
H A D | ir3_gallium.c | 86 "%u dwords, %u last-baryf, %u half, %u full, %u constlen, " in dump_shader_info() 93 v->info.max_half_reg + 1, v->info.max_reg + 1, v->constlen, in dump_shader_info() 223 if (v->constlen > compiler->max_const_safe) { in create_initial_variants() 235 if (v->constlen > compiler->max_const_safe) { in create_initial_variants()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_program.c | 85 uint8_t constlen; member 106 /* constlen is in units of 4 * vec4: */ in setup_stages() 107 assert(s[i].v->constlen % 4 == 0); in setup_stages() 108 s[i].constlen = s[i].v->constlen / 4; in setup_stages() 116 s[i].constlen = 0; in setup_stages() 143 s[VS].constlen = 66; in setup_stages() 144 s[FS].constlen = 128 - s[VS].constlen; in setup_stages() 148 s[FS].constoff = s[VS].constlen; in setup_stages() [all...] |
H A D | fd4_compute.c | 73 A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4)); in cs_program_emit()
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H A D | fd4_emit.c | 135 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_program.c | 155 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */ in fd3_program_emit() 156 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0; in fd3_program_emit() 216 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) | in fd3_program_emit() 219 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) | in fd3_program_emit() 243 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) | in fd3_program_emit() 245 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen - 1, 0))); in fd3_program_emit() 315 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) | in fd3_program_emit() 318 MAX2(fp->constlen in fd3_program_emit() [all...] |
H A D | fd3_emit.c | 143 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
H A D | fd5_compute.c | 80 assert(v->constlen % 4 == 0); in cs_program_emit() 81 unsigned constlen = v->constlen / 4; in cs_program_emit() local 83 OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */ in cs_program_emit()
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H A D | fd5_program.c | 158 uint8_t constlen; member 179 /* constlen is in units of 4 * vec4: */ in setup_stages() 180 assert(s[i].v->constlen % 4 == 0); in setup_stages() 181 s[i].constlen = s[i].v->constlen / 4; in setup_stages() 189 s[i].constlen = 0; in setup_stages() 220 constoff += s[i].constlen; in setup_stages() 356 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */ in fd5_program_emit() 360 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */ in fd5_program_emit() 364 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLE in fd5_program_emit() [all...] |
H A D | fd5_emit.c | 142 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
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/third_party/mesa3d/src/freedreno/common/ |
H A D | disasm.h | 46 int constlen; member
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/third_party/mesa3d/src/freedreno/computerator/ |
H A D | a6xx.c | 138 unsigned constlen = align(v->constlen, 4); in cs_program_emit() local 141 A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) | A6XX_HLSQ_CS_CNTL_ENABLED); in cs_program_emit() 292 size = MIN2(size + base, v->constlen) - base; in cs_const_emit()
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H A D | a4xx.c | 122 A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4)); in cs_program_emit() 215 size = MIN2(size + base, v->constlen) - base; in cs_const_emit()
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/third_party/mesa3d/src/freedreno/ir3/ |
H A D | ir3_shader.c | 165 /* NOTE: if relative addressing is used, we set constlen in in ir3_shader_assemble() 169 v->constlen = MAX2(v->constlen, info->max_const + 1); in ir3_shader_assemble() 171 if (v->constlen > ir3_const_state(v)->offsets.driver_param) in ir3_shader_assemble() 174 /* On a4xx and newer, constlen must be a multiple of 16 dwords even though in ir3_shader_assemble() 176 * regarding the shared constlen simpler. in ir3_shader_assemble() 179 v->constlen = align(v->constlen, 4); in ir3_shader_assemble() 575 /* Given an array of constlen's, decrease some of them so that the sum stays 609 /* Figures out which stages in the pipeline to use the "safe" constlen fo [all...] |
H A D | disasm-a3xx.c | 129 "%s- shaderdb: %u last-baryf, %d half, %d full, %u constlen\n", in print_stats() 133 DIV_ROUND_UP(ctx->stats->constlen, 4)); in print_stats() 488 ctx->stats->constlen = MAX2(ctx->stats->constlen, num); in disasm_field_cb()
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H A D | ir3_shader.h | 315 /* Whether this variant sticks to the "safe" maximum constlen, 566 unsigned constlen; member 869 * In order to use the same cmdstream, in particular constlen setup and const 881 /* Given a variant, calculate the maximum constlen it can have.
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H A D | ir3_compiler_nir.c | 960 /* NOTE: since relative addressing is used, make sure constlen is in emit_intrinsic_load_ubo() 964 ctx->so->constlen = in emit_intrinsic_load_ubo() 965 MAX2(ctx->so->constlen, in emit_intrinsic_load_ubo() 2074 * constlen in the compiler (to worst-case value) in emit_intrinsic() 2078 ctx->so->constlen = in emit_intrinsic() 2079 MAX2(ctx->so->constlen, in emit_intrinsic()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
H A D | fd6_program.c | 300 assert(state->vs->constlen >= state->bs->constlen); in setup_config_stateobj() 303 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) | in setup_config_stateobj() 307 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen))); in setup_config_stateobj() 310 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen))); in setup_config_stateobj() 313 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen))); in setup_config_stateobj() 315 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) | in setup_config_stateobj() 374 if (regid >= s->constlen)
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H A D | fd6_compute.c | 54 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) |
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H A D | fd6_const.c | 116 int size = MIN2(1 + regid, v->constlen) - regid; in emit_stage_tess_consts()
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/third_party/mesa3d/src/freedreno/vulkan/ |
H A D | tu_pipeline.h | 92 uint32_t constlen; member
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H A D | tu_pipeline.c | 410 size = MIN2(size + base, xs->constlen) - base; in tu_xs_get_immediates_packet_size_dwords() 464 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) | in tu6_emit_xs_config() 623 (16 * xs->constlen) - ubo_state->range[i].offset); in tu6_emit_xs() 640 size = MAX2(MIN2(size + base, xs->constlen) - base, 0); in tu6_emit_xs() 919 size = (MIN2(size + base, consumer->constlen) - base) * 4; in tu6_emit_link_map() 1646 uint32_t hs_param_dwords = MIN2((hs->constlen - hs_base) * 4, ARRAY_SIZE(hs_params)); in tu6_emit_geom_tess_consts() 1664 uint32_t ds_param_dwords = MIN2((ds->constlen - ds_base) * 4, ARRAY_SIZE(ds_params)); in tu6_emit_geom_tess_consts() 3214 link->constlen = v->constlen; in tu_pipeline_set_linkage() 3229 * the constlen fo in tu_pipeline_builder_parse_shader_stages() [all...] |
H A D | tu_cmd_buffer.c | 4616 if (const_state->offsets.driver_param >= link->constlen) in vs_params_offset() 4941 if (link->constlen <= offset) in tu_emit_compute_driver_params() 4945 (link->constlen - offset) * 4); in tu_emit_compute_driver_params()
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/third_party/mesa3d/src/freedreno/decode/ |
H A D | pgmdump2.c | 390 "%u half, %u full, %u constlen, " in decode_shader_descriptor_block() 394 full_regs, stats.constlen, stats.ss, stats.sy, 0, in decode_shader_descriptor_block()
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