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Searched refs:cdw (Results 1 - 25 of 47) sorted by relevance

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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h37 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
39 return cs->cdw + needed; in radeon_check_space()
46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
63 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_context_reg_seq()
80 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_context_reg_idx()
90 assert(cs->cdw + 4 <= cs->max_dw); in radeon_set_context_reg_rmw()
101 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_sh_reg_seq()
119 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_sh_reg_idx()
135 assert(cs->cdw + 3 <= cs->max_dw); in gfx10_set_sh_reg_idx3()
146 assert(cs->cdw in radeon_set_uconfig_reg_seq()
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H A Dradv_sdma_copy_image.c109 while (cmd_buffer->cs->cdw & ib_pad_dw_mask) in radv_sdma_v4_v5_copy_image_to_buffer()
112 assert(cmd_buffer->cs->cdw <= cdw_max); in radv_sdma_v4_v5_copy_image_to_buffer()
179 while (cmd_buffer->cs->cdw & ib_pad_dw_mask) in radv_sdma_v4_v5_copy_image_to_buffer()
182 assert(cmd_buffer->cs->cdw <= cdw_max); in radv_sdma_v4_v5_copy_image_to_buffer()
H A Dradv_radeon_winsys.h105 unsigned cdw; /* Number of used dwords. */ member
313 cs->buf[cs->cdw++] = value; in radeon_emit()
319 memcpy(cs->buf + cs->cdw, values, count * 4); in radeon_emit_array()
320 cs->cdw += count; in radeon_emit_array()
H A Dradv_perfcounter.c607 uint32_t *skip_dwords = cs->buf + cs->cdw; in radv_pc_stop_and_sample()
640 *skip_dwords = cs->buf + cs->cdw - skip_dwords - 1; in radv_pc_stop_and_sample()
690 uint32_t *skip_dwords = cs->buf + cs->cdw; in radv_pc_begin_query()
710 *skip_dwords = cs->buf + cs->cdw - skip_dwords - 1; in radv_pc_begin_query()
724 assert(cmd_buffer->cs->cdw <= cdw_max); in radv_pc_begin_query()
758 assert(cmd_buffer->cs->cdw <= cdw_max); in radv_pc_end_query()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c51 unsigned cdw; member
305 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
311 uint64_t ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()
322 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
328 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw; in radv_amdgpu_cs_grow()
334 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
338 ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()
353 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
361 while (!cs->base.cdw || (c in radv_amdgpu_cs_grow()
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/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_cs.h49 assert(size <= (cs_copy->current.max_dw - cs_copy->current.cdw)); \
75 cs_copy->current.buf[cs_copy->current.cdw++] = (value); \
99 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
100 cs_copy->current.cdw += (count); \
123 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
124 cs_copy->current.cdw += (count); \
/third_party/libdrm/radeon/
H A Dradeon_cs.h55 unsigned cdw; member
117 cs->packets[cs->cdw++] = dword; in radeon_cs_write_dword()
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t)); in radeon_cs_write_qword()
126 cs->cdw += 2; in radeon_cs_write_qword()
135 memcpy(cs->packets + cs->cdw, data, size * 4); in radeon_cs_write_table()
136 cs->cdw += size; in radeon_cs_write_table()
H A Dradeon_cs_gem.c296 if (cs->cdw + ndw > cs->ndw) { in cs_gem_begin()
300 tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF); in cs_gem_begin()
366 blob = bof_blob(cs->cdw * 4, cs->packets); in cs_gem_dump_bof()
431 while (cs->cdw & 7) in cs_gem_emit()
437 csg->chunks[0].length_dw = cs->cdw; in cs_gem_emit()
489 cs->cdw = 0; in cs_gem_erase()
509 for (i = 0; i < cs->cdw; i++) { in cs_gem_print()
H A Dradeon_cs_int.h15 unsigned cdw; member
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h131 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
145 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
161 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
170 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
184 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
200 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
H A Dr600_pipe.h625 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); in r600_emit_command_buffer()
626 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw); in r600_emit_command_buffer()
627 cs->current.cdw += cb->num_dw; in r600_emit_command_buffer()
992 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; in radeon_compute_set_context_reg_seq()
998 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_ctl_const_seq()
H A Dradeon_vce.h39 #define RVCE_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
41 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
46 #define RVCE_END() *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; }
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dradeon_vcn.c36 sq->ib_checksum = &cs->current.buf[cs->current.cdw]; in rvcn_sq_header()
38 sq->ib_total_size_in_dw = &cs->current.buf[cs->current.cdw]; in rvcn_sq_header()
59 end = &cs->current.buf[cs->current.cdw]; in rvcn_sq_tail()
H A Dsi_debug.c53 saved->num_dw = cs->prev_dw + cs->current.cdw; in si_save_cs()
60 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4); in si_save_cs()
61 buf += cs->prev[i].cdw; in si_save_cs()
63 memcpy(buf, cs->current.buf, cs->current.cdw * 4); in si_save_cs()
366 if (begin < chunk->cdw) { in si_parse_current_ib()
367 ac_parse_ib_chunk(f, chunk->buf + begin, MIN2(end, chunk->cdw) - begin, last_trace_id, in si_parse_current_ib()
371 if (end <= chunk->cdw) in si_parse_current_ib()
374 if (begin < chunk->cdw) in si_parse_current_ib()
377 begin -= MIN2(begin, chunk->cdw); in si_parse_current_ib()
378 end -= chunk->cdw; in si_parse_current_ib()
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H A Dradeon_uvd_enc_1_1.c38 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
41 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
50 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \
79 enc->cs.current.buf[enc->cs.current.cdw] = 0; in radeon_uvd_enc_output_one_byte()
80 enc->cs.current.buf[enc->cs.current.cdw] |= in radeon_uvd_enc_output_one_byte()
86 enc->cs.current.cdw++; in radeon_uvd_enc_output_one_byte()
162 enc->cs.current.cdw++; in radeon_uvd_enc_flush_headers()
214 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_uvd_enc_task_info()
394 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_uvd_enc_nalu_sps_hevc()
489 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw in radeon_uvd_enc_nalu_pps_hevc()
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H A Dradeon_vcn_enc_1_2.c85 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_task_info()
270 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps()
352 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps_hevc()
465 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_prefix()
509 unsigned *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sei()
520 unsigned position = enc->cs.current.cdw; in radeon_enc_nalu_sei()
574 unsigned position2 = enc->cs.current.cdw; in radeon_enc_nalu_sei()
582 enc->cs.current.cdw = position; in radeon_enc_nalu_sei()
594 enc->cs.current.cdw = position2; in radeon_enc_nalu_sei()
612 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw in radeon_enc_nalu_pps()
[all...]
H A Dsi_build_pm4.h43 unsigned __cs_num = __cs->current.cdw; \
50 __cs_num = __cs->current.cdw; \
56 __cs->current.cdw = __cs_num; \
57 assert(__cs->current.cdw <= __cs->current.max_dw); \
H A Dradeon_vcn_enc_2_0.c94 cdw_start = enc->cs.current.cdw; in radeon_enc_slice_header_hevc()
205 cdw_filled = enc->cs.current.cdw - cdw_start; in radeon_enc_slice_header_hevc()
234 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps_hevc()
337 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_pps_hevc()
H A Dradeon_vcn_enc.h131 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
134 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
143 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \
H A Dradeon_vce.h34 #define RVCE_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
37 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
46 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_cs.c799 rcs->current.cdw = 0; in amdgpu_get_new_ib()
833 *ib->ptr_ib_size = rcs->current.cdw | in amdgpu_set_ib_size()
836 *ib->ptr_ib_size = rcs->current.cdw; in amdgpu_set_ib_size()
844 ib->used_ib_space += rcs->current.cdw * 4; in amdgpu_ib_finalize()
846 ib->max_ib_size = MAX2(ib->max_ib_size, rcs->prev_dw + rcs->current.cdw); in amdgpu_ib_finalize()
1098 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()
1101 unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw; in amdgpu_cs_check_space()
1106 if (rcs->current.max_dw - rcs->current.cdw >= dw) in amdgpu_cs_check_space()
1145 while ((rcs->current.cdw & ib_pad_dw_mask) != ib_pad_dw_mask - 3) in amdgpu_cs_check_space()
1151 uint32_t *new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw in amdgpu_cs_check_space()
[all...]
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_cs.c457 assert(rcs->current.cdw == 0); in radeon_drm_cs_validate()
458 if (rcs->current.cdw != 0) { in radeon_drm_cs_validate()
468 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()
469 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()
593 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
596 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
605 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
608 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
613 while (rcs->current.cdw & 15) in radeon_drm_cs_flush()
620 if (rcs->current.cdw > rc in radeon_drm_cs_flush()
[all...]
/third_party/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_encode.h60 state->buf[state->cdw++] = dword; in virgl_encoder_write_dword()
66 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
67 state->cdw += 2; in virgl_encoder_write_qword()
74 memcpy(state->buf + state->cdw, ptr, len); in virgl_encoder_write_block()
77 uint8_t *mp = (uint8_t *)(state->buf + state->cdw); in virgl_encoder_write_block()
81 state->cdw += (len + 3) / 4; in virgl_encoder_write_block()
H A Dvirgl_transfer_queue.c329 uint32_t prior_num_dwords = cbuf->cdw; in virgl_transfer_queue_clear()
330 cbuf->cdw = 0; in virgl_transfer_queue_clear()
337 cbuf->cdw = prior_num_dwords; in virgl_transfer_queue_clear()
/third_party/mesa3d/src/gallium/include/winsys/
H A Dradeon_winsys.h191 unsigned cdw; /* Number of used dwords. */ member
712 return cs && (cs->prev_dw + cs->current.cdw > num_dw); in radeon_emitted()
717 cs->current.buf[cs->current.cdw++] = value; in radeon_emit()
723 memcpy(cs->current.buf + cs->current.cdw, values, count * 4); in radeon_emit_array()
724 cs->current.cdw += count; in radeon_emit_array()

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