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Searched refs:blk_w (Results 1 - 20 of 20) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c47 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w) in minify_as_blocks() argument
50 return DIV_ROUND_UP(width, blk_w); in minify_as_blocks()
120 unsigned copy_width = DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w); in si_sdma_v4_v5_copy_texture()
156 unsigned tiled_width = DIV_ROUND_UP(tiled->buffer.b.b.width0, tiled->surface.blk_w); in si_sdma_v4_v5_copy_texture()
247 unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0, 0, sdst->surface.blk_w); in cik_sdma_copy_texture()
248 unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0, 0, ssrc->surface.blk_w); in cik_sdma_copy_texture()
249 unsigned copy_width = DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w); in cik_sdma_copy_texture()
H A Dradeon_vcn_dec_jpeg.c50 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in radeon_jpeg_get_decode_param()
H A Dsi_texture.c153 (box->y / tex->surface.blk_h * pitch + box->x / tex->surface.blk_w) * in si_texture_get_offset()
168 box->x / tex->surface.blk_w) * in si_texture_get_offset()
548 tex->surface.blk_w, false, 0, desc); in si_set_tex_bo_metadata()
H A Dradeon_uvd.c1442 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w; in si_uvd_set_dt_surfaces()
1485 msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w; in si_uvd_set_dt_surfaces()
H A Dradeon_vcn_dec.c1924 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in rvcn_dec_message_decode()
1925 decode->dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w; in rvcn_dec_message_decode()
1951 decode->db_pitch_uv = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w; in rvcn_dec_message_decode()
H A Dsi_descriptors.c394 epitch = (epitch + 1) / tex->surface.blk_w - 1; in si_set_mutable_tex_desc_fields()
/third_party/libdrm/radeon/
H A Dradeon_surface.c176 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in surf_minify()
585 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in eg_surf_minify()
1436 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1440 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1486 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify_2d()
[all...]
H A Dradeon_surface.h114 uint32_t blk_w; member
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_surface.c42 if (!surf->blk_w || !surf->blk_h) in radv_amdgpu_surface_sanity()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c103 surf_drm->blk_w = util_format_get_blockwidth(tex->format); in surf_winsys_to_drm()
183 surf_ws->blk_w = surf_drm->blk_w; in surf_drm_to_winsys()
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c76 surf->blk_w = util_format_get_blockwidth(tex->format); in amdgpu_surface_init()
/third_party/mesa3d/src/mesa/main/
H A Dtexcompress_astc.cpp1818 unsigned blk_w, blk_h;
1819 _mesa_get_format_block_size(format, &blk_w, &blk_h);
1822 unsigned x_blocks = (src_width + blk_w - 1) / blk_w;
1825 Decoder dec(blk_w, blk_h, 1, srgb, true);
1835 unsigned dst_blk_w = MIN2(blk_w, src_width - x*blk_w);
1841 (x * blk_w + sub_x) * 4;
1842 const uint16_t *src = &block_out[(sub_y * blk_w + sub_x) * 4];
/third_party/mesa3d/src/amd/common/
H A Dac_surface.c685 AddrSurfInfoIn->basePitch *= surf->blk_w; in gfx6_compute_level()
881 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 && in get_display_flag()
884 if (surf->blk_w == 2 && surf->blk_h == 1) in get_display_flag()
1018 * blk_w, blk_h, bpe, flags.
1044 compressed = surf->blk_w == 4 && surf->blk_h == 4; in gfx6_compute_surface()
1767 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch && in gfx9_compute_miptree()
1770 surf->u.gfx9.surf_pitch = align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe); in gfx9_compute_miptree()
1772 MAX2(surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1); in gfx9_compute_miptree()
1780 surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w); in gfx9_compute_miptree()
1789 surf->u.gfx9.pitch[i] = align(mip_info[i].pitch / surf->blk_w, alignmen in gfx9_compute_miptree()
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H A Dac_surface.h309 uint8_t blk_w : 4; member
H A Dac_surface_modifier_test.c249 .blk_w = 1, in test_modifier()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_sdma_copy_image.c81 unsigned copy_width = DIV_ROUND_UP(image->info.width, image->planes[0].surface.blk_w); in radv_sdma_v4_v5_copy_image_to_buffer()
H A Dradv_image.c1361 0, image->planes[0].surface.blk_w, false, false, false, false, in radv_query_opaque_metadata()
1623 image->planes[i].surface.blk_w = vk_format_get_blockwidth(format); in radv_image_reset_layout()
1944 uint32_t blk_w; in radv_image_view_make_descriptor() local
1955 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0); in radv_image_view_make_descriptor()
1956 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * in radv_image_view_make_descriptor()
1983 iview->vk.base_mip_level, blk_w, is_stencil, is_storage_image, in radv_image_view_make_descriptor()
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_cb_texture.c507 unsigned blk_w, blk_h; in st_MapTextureImage() local
508 _mesa_get_format_block_size(texImage->TexFormat, &blk_w, &blk_h); in st_MapTextureImage()
519 (x / blk_w) * block_size; in st_MapTextureImage()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_texture.c194 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
824 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " in r600_print_texture_info()
828 rtex->resource.b.b.depth0, rtex->surface.blk_w, in r600_print_texture_info()
H A Dradeon_uvd.c1209 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w; in ruvd_set_dt_surfaces()

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