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Searched refs:binning (Results 1 - 25 of 29) sorted by relevance

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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_disk_cache.c44 * for this reason, because binning pass variants share const_state with
176 v->binning = NULL; in ir3_retrieve_variant()
185 v->binning = rzalloc_size(v, sizeof(*v->binning)); in ir3_retrieve_variant()
186 v->binning->id = 0; in ir3_retrieve_variant()
187 v->binning->compiler = compiler; in ir3_retrieve_variant()
188 v->binning->binning_pass = true; in ir3_retrieve_variant()
189 v->binning->nonbinning = v; in ir3_retrieve_variant()
190 v->binning->key = v->key; in ir3_retrieve_variant()
191 v->binning in ir3_retrieve_variant()
[all...]
H A Dir3_shader.c312 * creating binning pass shader, it is link to corresponding normal
313 * (non-binning) variant.
319 /* hang the binning variant off it's non-binning counterpart instead in alloc_variant()
408 v->binning = alloc_variant(shader, key, v, mem_ctx); in create_variant()
409 if (!v->binning) in create_variant()
411 v->binning->disasm_info.write_disasm = write_disasm; in create_variant()
435 if (needs_binning_variant(v) && !compile_variant(shader, v->binning)) in create_variant()
486 v = v->binning; in ir3_shader_get_variant()
H A Dir3_shader.h271 * in hw (two sided color), binning-pass vertex shader, etc.
502 * which is pointed to by so->binning:
506 struct ir3_shader_variant *binning; member
799 /* Currently we do not do binning for tess. And for GS there is no
801 * the binning pass.
870 * emit, for both binning and draw pass (a6xx+), the binning pass re-uses it's
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_emit.h59 /* in binning pass, we don't have real frag shader, so we
84 /* We use nonbinning VS during binning when TFB is enabled because that in fd5_emit_get_vp()
101 /* use dummy stateobj to simplify binning vs non-binning: */ in fd5_emit_get_fp()
162 fd5_emit_render_cntl(struct fd_context *ctx, bool blit, bool binning) assert_dt
165 binning ? ctx->batch->binning : ctx->batch->draw;
178 COND(binning, A5XX_RB_RENDER_CNTL_BINNING_PASS) |
179 COND(binning, A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE) |
185 COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PAS
[all...]
H A Dfd5_draw.c120 /* figure out whether we need to disable LRZ write for binning
130 /* and now binning pass: */
135 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
H A Dfd5_gmem.c266 /* workaround: Like on a3xx, hw binning and scissor optimization in use_hw_binning()
269 * Disable binning if scissor optimization is used. in use_hw_binning()
376 /* emit IB to binning drawcmds: */
377 fd5_emit_ib(ring, batch->binning);
427 /* Enable stream output for the first pass (likely the binning). */
434 /* Disable stream output after binning, since each VS output should get
448 /* XXX If we're in gmem mode but not doing HW binning, then after the first
767 /* Enable stream output, since there's no binning pass to put it in. */
/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_gallium.c146 if (v->binning) { in ir3_shader_variant()
147 upload_shader_variant(v->binning); in ir3_shader_variant()
148 dump_shader_info(v->binning, debug); in ir3_shader_variant()
228 /* For vertex shaders, also compile initial binning pass shader: */ in create_initial_variants()
429 if (v->binning && v->binning->bo) { in ir3_shader_state_delete()
430 fd_bo_del(v->binning->bo); in ir3_shader_state_delete()
431 v->binning->bo = NULL; in ir3_shader_state_delete()
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_program.c151 /* compile binning variant now */ in fd2_vp_state_create()
214 bool binning = (ctx->batch && ring == ctx->batch->binning); in fd2_program_emit() local
220 if (!binning) { in fd2_program_emit()
249 binning ? &ctx->batch->shader_patches : NULL); in fd2_program_emit()
259 if (vp->writes_psize && !binning) in fd2_program_emit()
H A Dfd2_draw.c76 fd2_emit_vertex_bufs(ctx->batch->binning, 0x78, bufs, vtx->num_elements);
82 unsigned index_offset, bool binning) assert_dt
98 * draws that read binning data
125 /* binning shader will take offset from C64 */
126 if (binning && is_a20x(ctx->screen)) {
136 if (binning || info->mode == PIPE_PRIM_POINTS)
205 draw_impl(ctx, pinfo, &draw, ctx->batch->binning, index_offset, true);
213 draw_impl(ctx, pinfo, pdraw, ctx->batch->binning, index_offset, true);
H A Dir2_nir.c834 /* fragcoord.zw and a20x hw binning outputs */
836 extra_position_exports(struct ir2_context *ctx, bool binning) in extra_position_exports() argument
840 if (ctx->f->fragcoord < 0 && !binning) in extra_position_exports()
861 if (ctx->f->fragcoord >= 0 && !binning) { in extra_position_exports()
873 if (!binning) in extra_position_exports()
1056 /* kill non-position outputs for binning variant */ in cleanup_binning()
1098 ir2_nir_compile(struct ir2_context *ctx, bool binning) in ir2_nir_compile() argument
1106 if (binning) in ir2_nir_compile()
1179 extra_position_exports(ctx, binning); in ir2_nir_compile()
H A Dir2.c445 bool binning = !fp && so->type == MESA_SHADER_VERTEX; in ir2_compile() local
456 ir2_nir_compile(&ctx, binning); in ir2_compile()
471 assemble(&ctx, binning); in ir2_compile()
H A Dir2_private.h188 void assemble(struct ir2_context *ctx, bool binning);
190 void ir2_nir_compile(struct ir2_context *ctx, bool binning);
H A Dir2_assemble.c272 /* export32 instr for a20x hw binning has this bit set.. in fill_instr()
357 assemble(struct ir2_context *ctx, bool binning) in assemble() argument
H A Dfd2_emit.c192 struct fd_ringbuffer *ring = ctx->batch->binning; in fd2_emit_state_binning()
194 /* subset of fd2_emit_state needed for hw binning on a20x */ in fd2_emit_state_binning()
345 /* set viewport in C65/C66, for a20x hw binning and fragcoord.z */ in fd2_emit_state()
H A Dfd2_gmem.c76 /* only a20x hw binning is implement in use_hw_binning()
576 * a specific pattern of ALLOC/EXEC CF pairs for the hw binning exports
593 /* initialize shader constants for the binning memexport */
631 * to clip at binning stage: only use center 6x6
632 * TODO: set the z parameters too so that hw binning
656 fd2_emit_ib(ring, batch->binning);
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_util.c211 tiling->binning = (tiling->tile_count.width * tiling->tile_count.height) > 2; in tu_tiling_config_update_binning()
214 tiling->binning = true; in tu_tiling_config_update_binning()
217 tiling->binning = false; in tu_tiling_config_update_binning()
219 tiling->binning = false; in tu_tiling_config_update_binning()
H A Dtu_device.h367 /* Whether binning should be used for gmem rendering using this framebuffer. */
368 bool binning; member
370 /* Whether binning could be used for gmem rendering using this framebuffer. */
H A Dtu_pipeline.c1725 /* Don't use the binning pass variant when GS is present because we don't in tu6_emit_program()
1726 * support compiling correct binning pass variants with GS. in tu6_emit_program()
1909 .fetch_cnt = used_attrs_count, /* decode_cnt for binning pass ? */ in tu6_emit_vertex_input()
2365 if (variant->binning) { in tu_pipeline_allocate_cs()
2367 tu_xs_get_additional_cs_size_dwords(variant->binning); in tu_pipeline_allocate_cs()
3040 tu_append_executable(pipeline, vs->binning, NULL); in tu_pipeline_builder_compile_shaders()
3041 variant = vs->binning; in tu_pipeline_builder_compile_shaders()
3227 * Note also that this always uses the full VS even in binning pass. The in tu_pipeline_builder_parse_shader_stages()
3228 * binning pass variant has the same const layout as the full VS, and in tu_pipeline_builder_parse_shader_stages()
3230 * for the binning pas in tu_pipeline_builder_parse_shader_stages()
[all...]
/third_party/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_batch.c73 /* a6xx+ re-uses draw rb for both draw and binning pass: */ in batch_init()
75 batch->binning = alloc_ring(batch, 0x100000, 0); in batch_init()
156 if (batch->binning) { in cleanup_submit()
157 fd_ringbuffer_del(batch->binning); in cleanup_submit()
158 batch->binning = NULL; in cleanup_submit()
H A Dfreedreno_batch.h49 * ringbuffers used for binning, draw, and gmem cmds, list of associated
168 * on whether we using binning or not:
188 /* Keep track of pointer to start of MEM exports for a20x binning shaders
201 /** binning pass cmdstream: */
202 struct fd_ringbuffer *binning; member
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_draw.c154 /* and now binning pass: */
159 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
H A Dfd3_gmem.c146 /* workaround: combining scissor optimization and hw binning in use_hw_binning()
148 * between binning pass and rendering pass, wrt. where the hw in use_hw_binning()
155 * benefit much from binning pass). in use_hw_binning()
157 * So for now just disable binning if scissor optimization is in use_hw_binning()
172 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
891 /* emit IB to binning drawcmds: */
892 fd3_emit_ib(ring, batch->binning);
976 /* emit hw binning pass: */
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_draw.c167 /* and now binning pass: */
172 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
H A Dfd4_gmem.c149 /* workaround: Like on a3xx, hw binning and scissor optimization in use_hw_binning()
152 * Disable binning if scissor optimization is used. in use_hw_binning()
653 /* emit IB to binning drawcmds: */
654 fd4_emit_ib(ring, batch->binning);
704 /* emit hw binning pass: */
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_gmem.c349 bool binning) in update_render_cntl()
378 if (binning) in update_render_cntl()
726 /* emit IB to binning drawcmds: */
840 /* enable stream-out during binning pass: */
875 /* no binning pass, so enable stream-out for draw pass:: */
348 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning) update_render_cntl() argument

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