| /third_party/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| H A D | nv50_program.c | 111 prog->vp.bfc[info->out[i].si] = i; in nv50_vertprog_assign_slots()
179 prog->vp.bfc[info->in[i].si] = j; in nv50_fragprog_assign_slots()
216 if (prog->vp.bfc[i] < 0xff) in nv50_fragprog_assign_slots()
217 prog->fp.colors += bitcount4(prog->in[prog->vp.bfc[i]].mask) << 16; in nv50_fragprog_assign_slots()
375 prog->vp.bfc[0] = 0xff; in nv50_program_translate()
376 prog->vp.bfc[1] = 0xff; in nv50_program_translate()
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| H A D | nv50_shader_state.c | 446 uint8_t bfc, ffc; in nv50_fp_linkage_validate() local
448 bfc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_BFC0_ID__MASK) in nv50_fp_linkage_validate()
450 if (nv50->rast->pipe.light_twoside == ((ffc == bfc) ? 0 : 1)) in nv50_fp_linkage_validate()
475 n = vp->vp.bfc[i]; in nv50_fp_linkage_validate()
476 if (fp->vp.bfc[i] >= fp->in_nr) in nv50_fp_linkage_validate()
478 m = nv50_vec4_map(map, m, lin, &fp->in[fp->vp.bfc[i]], in nv50_fp_linkage_validate()
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| H A D | nv50_program.h | 81 ubyte bfc[2]; /* indices into varying for FFC (FP) or BFC (VP) */ member
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| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | sbrdsp_neon.S | 313 bfc r3, #9, #23
328 bfc r3, #9, #23
361 bfc r3, #9, #23
376 bfc r3, #9, #23
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| H A D | synth_filter_neon.S | 29 bfc r12, #9, #23
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| H A D | rdft_neon.S | 120 bfc r2, #0, #31
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_simulator.c | 397 int bfc = simpenrose_do_binning(exec.ct0ca, exec.ct0ea); in vc4_simulator_submit_cl_ioctl() local
398 if (bfc != 1) { in vc4_simulator_submit_cl_ioctl()
400 bfc); in vc4_simulator_submit_cl_ioctl()
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| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 1340 Format(instr, "bfc'cond 'rd, 'f"); in DecodeType3()
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 565 void bfc(Register dst, int lsb, int width, Condition cond = al);
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| H A D | macro-assembler-arm.cc | 619 bfc(dst, lsb, width, cond); in Bfc()
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| H A D | assembler-arm.cc | 1876 // bfc dst, #lsb, #width
1877 void Assembler::bfc(Register dst, int lsb, int width, Condition cond) { in bfc() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 2063 void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
2064 void bfc(Register rd, uint32_t lsb, uint32_t width) { in bfc() function in vixl::aarch32::Assembler
2065 bfc(al, rd, lsb, width); in bfc()
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| H A D | disasm-aarch32.h | 684 void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
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| H A D | assembler-aarch32.cc | 3194 void Assembler::bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width) { in bfc() function in vixl::aarch32::Assembler
3218 Delegate(kBfc, &Assembler::bfc, cond, rd, lsb, width); in bfc()
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| H A D | disasm-aarch32.cc | 1279 void Disassembler::bfc(Condition cond, in bfc() function in vixl::aarch32::Disassembler
9359 bfc(CurrentCond(), Register(rd), lsb, width); in DecodeT32()
[all...] |
| H A D | macro-assembler-aarch32.h | 1499 bfc(cond, rd, lsb, width); in MacroAssembler()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 562 COMPARE(bfc(w25, 13, 8), "bfc w25, #13, #8"); in TEST()
563 COMPARE(bfc(x26, 14, 7), "bfc x26, #14, #7"); in TEST()
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 1137 __ bfc(i.OutputRegister(), i.InputInt8(1), i.InputInt8(2)); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 806 void bfc(const Register& rd, unsigned lsb, unsigned width) { in bfc() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 1200 bfc(rd, lsb, width); in Bfc()
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