| /third_party/libdrm/radeon/ |
| H A D | radeon_surface.c | 675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
760 switch (surf->bankw) { in eg_surface_sanity()
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
905 /* compute best tile_split, bankw, bankh, mtilea
919 surf->bankw = 1; in eg_surface_best()
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
978 /* bankw or bankh greater than 1 increase alignment requirement, not in eg_surface_best()
979 * sure if it's worth using smaller bankw & bankh to stick with 2D in eg_surface_best()
995 /* use bankw of 1 to minimize width alignment, might be interesting to in eg_surface_best()
998 surf->bankw in eg_surface_best()
[all...] |
| H A D | radeon_surface.h | 124 * overridden (things lile bankw/bankh on evergreen for
130 uint32_t bankw; member
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | radeon_video.c | 162 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh; in rvid_join_surfaces()
177 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw; in rvid_join_surfaces()
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| H A D | r600_texture.c | 284 metadata->u.legacy.bankw = surface->u.legacy.bankw; in r600_texture_init_metadata()
300 surf->u.legacy.bankw = metadata->u.legacy.bankw; in r600_surface_import_metadata()
609 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw; in r600_texture_get_fmask_info()
834 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, " in r600_print_texture_info()
836 rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw, in r600_print_texture_info()
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| H A D | evergreen_state.c | 736 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; in evergreen_fill_tex_resource_words() local
815 bankw = tmp->surface.u.legacy.bankw; in evergreen_fill_tex_resource_words()
819 bankw = eg_bank_wh(bankw); in evergreen_fill_tex_resource_words()
903 S_03001C_BANK_WIDTH(bankw) | in evergreen_fill_tex_resource_words()
1126 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; in evergreen_set_color_surface_common() local
1164 bankw = rtex->surface.u.legacy.bankw; in evergreen_set_color_surface_common()
1172 bankw in evergreen_set_color_surface_common()
1362 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; evergreen_init_depth_surface() local
[all...] |
| H A D | radeon_uvd.c | 1241 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw); in ruvd_set_dt_surfaces()
1246 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw)); in ruvd_set_dt_surfaces()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 151 surf_drm->bankw = surf_ws->u.legacy.bankw; in surf_winsys_to_drm()
193 surf_ws->u.legacy.bankw = surf_drm->bankw; in surf_drm_to_winsys()
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| H A D | radeon_drm_bo.c | 900 surf->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_get_metadata()
923 md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_get_metadata()
951 args.tiling_flags |= (surf->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) << in radeon_bo_set_metadata()
976 args.tiling_flags |= (md->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) << in radeon_bo_set_metadata()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface.h | 114 unsigned bankw : 4; /* max 8 */ member
326 * they will be treated as hints (e.g. bankw, bankh) and might be
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| H A D | ac_surface.c | 914 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
1171 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && in gfx6_compute_surface()
1176 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw; in gfx6_compute_surface()
2638 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in ac_surface_set_bo_metadata()
2691 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw)); in ac_surface_get_bo_metadata()
3082 " Layout: size=%" PRIu64 ", alignment=%u, bankw=%u, bankh=%u, " in ac_surface_print_info()
3085 surf->u.legacy.bankw, surf->u.legacy.bankh, in ac_surface_print_info()
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_radeon_winsys.h | 145 unsigned bankw; member
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| H A D | radv_image.c | 435 surface->u.legacy.bankw = md->u.legacy.bankw; in radv_patch_surface_from_metadata()
1396 metadata->u.legacy.bankw = surface->u.legacy.bankw; in radv_init_metadata()
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| /third_party/mesa3d/src/gallium/include/winsys/ |
| H A D | radeon_winsys.h | 223 unsigned bankw; member
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| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_bo.c | 911 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in radv_amdgpu_winsys_bo_set_metadata()
959 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in radv_amdgpu_winsys_bo_get_metadata()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | radeon_uvd.c | 1474 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw); in si_uvd_set_dt_surfaces()
1479 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw)); in si_uvd_set_dt_surfaces()
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