Searched refs:and_mask (Results 1 - 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/spirv-tools/source/opt/ |
| H A D | amd_ext_to_khr.cpp | 313 // %and_mask = OpBitwiseOr %uint %uint_x %uint_mask_extend
314 // %and = OpBitwiseAnd %uint %id %and_mask
364 Instruction* and_mask = ir_builder.AddBinaryOp(uint_type_id, SpvOpBitwiseOr, in ReplaceSwizzleInvocationsMasked() local
367 uint_type_id, SpvOpBitwiseAnd, id->result_id(), and_mask->result_id()); in ReplaceSwizzleInvocationsMasked()
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| H A D | amd_ext_to_khr.cpp | 313 // %and_mask = OpBitwiseOr %uint %uint_x %uint_mask_extend
314 // %and = OpBitwiseAnd %uint %id %and_mask
364 Instruction* and_mask = ir_builder.AddBinaryOp(uint_type_id, SpvOpBitwiseOr, in ReplaceSwizzleInvocationsMasked() local
367 uint_type_id, SpvOpBitwiseAnd, id->result_id(), and_mask->result_id()); in ReplaceSwizzleInvocationsMasked()
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| /third_party/spirv-tools/source/opt/ |
| H A D | amd_ext_to_khr.cpp | 315 // %and_mask = OpBitwiseOr %uint %uint_x %uint_mask_extend
316 // %and = OpBitwiseAnd %uint %id %and_mask
366 Instruction* and_mask = ir_builder.AddBinaryOp( in ReplaceSwizzleInvocationsMasked() local
370 id->result_id(), and_mask->result_id()); in ReplaceSwizzleInvocationsMasked()
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| /third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm/crypto/bn/ |
| H A D | rsaz-avx2.s | 78 vmovdqu L$and_mask(%rip),%ymm15
753 vmovdqu L$and_mask(%rip),%ymm15
1734 L$and_mask:
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| /third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm_avx2/crypto/bn/ |
| H A D | rsaz-avx2.s | 78 vmovdqu L$and_mask(%rip),%ymm15
753 vmovdqu L$and_mask(%rip),%ymm15
1734 L$and_mask:
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| /third_party/mesa3d/src/amd/llvm/ |
| H A D | ac_llvm_build.c | 3379 static inline unsigned ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask) in ds_pattern_bitmode() argument
3381 assert(and_mask < 32 && or_mask < 32 && xor_mask < 32); in ds_pattern_bitmode()
3382 return and_mask | (or_mask << 5) | (xor_mask << 10); in ds_pattern_bitmode()
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| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_instruction_selection.cpp | 237 unsigned and_mask = mask & 0x1f; in emit_masked_swizzle() local
243 if (and_mask == 0x1f && or_mask < 4 && xor_mask < 4) { in emit_masked_swizzle()
248 } else if (and_mask == 0x1f && !or_mask && xor_mask == 8) { in emit_masked_swizzle()
250 } else if (and_mask == 0x1f && !or_mask && xor_mask == 0xf) { in emit_masked_swizzle()
252 } else if (and_mask == 0x1f && !or_mask && xor_mask == 0x7) { in emit_masked_swizzle()
254 } else if (ctx->options->gfx_level >= GFX10 && (and_mask & 0x18) == 0x18 && or_mask < 8 && in emit_masked_swizzle()
259 ret.instr->dpp8().lane_sel[i] = (((i & and_mask) | or_mask) ^ xor_mask) & 0x7; in emit_masked_swizzle()
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