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Searched refs:addr_reg (Results 1 - 21 of 21) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_export.cpp255 PVirtualValue addr_reg = nullptr; variable
282 addr_reg = vf.src_from_string(addr_str);
283 assert(addr_reg && addr_reg->as_register());
288 return new ScratchIOInstr(value, addr_reg->as_register(), align, align_offset, writemask, array_size);
H A Dsfn_instr_fetch.cpp572 auto addr_reg = vf.src_from_string(addrstr)->as_register(); in from_string() local
601 addr_reg, addr_offset_val, in from_string()
674 auto addr_reg = vf.src_from_string(addrstr); in from_string() local
681 return new LoadFromScratch( dest, dst_swz, addr_reg, size); in from_string()
H A Dsfn_shader.cpp1136 auto addr_reg = addr->as_register(); in load_uniform_indirect() local
1145 auto ir = new LoadFromBuffer(dest, {0,1,2,3}, addr_reg, offset, buffer_id, in load_uniform_indirect()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/
H A Dsfn_valuefactory_test.cpp156 auto addr_reg = factory->src(addr, 0); in TEST_F() local
166 EXPECT_EQ(*regx_addr, *addr_reg); in TEST_F()
174 EXPECT_EQ(*regy_addr, *addr_reg); in TEST_F()
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dinstruction-selector-mips.cc332 InstructionOperand addr_reg = g.TempRegister(); in VisitLoadTransform() local
333 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg, in VisitLoadTransform()
335 // Emit desired load opcode, using temp addr_reg. in VisitLoadTransform()
337 g.DefineAsRegister(node), addr_reg, g.TempImmediate(0)); in VisitLoadTransform()
384 InstructionOperand addr_reg = g.TempRegister(); in VisitLoad() local
385 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg, in VisitLoad()
387 // Emit desired load opcode, using temp addr_reg. in VisitLoad()
389 g.DefineAsRegister(node), addr_reg, g.TempImmediate(0)); in VisitLoad()
466 InstructionOperand addr_reg = g.TempRegister(); in VisitStore() local
467 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg, in VisitStore()
1442 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedLoad() local
1498 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedStore() local
1936 InstructionOperand addr_reg = g.TempRegister(); VisitWord32AtomicLoad() local
1977 InstructionOperand addr_reg = g.TempRegister(); VisitWord32AtomicStore() local
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/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc400 InstructionOperand addr_reg = g.TempRegister(); in EmitLoad() local
402 addr_reg, g.UseRegister(index), g.UseRegister(base)); in EmitLoad()
403 // Emit desired load opcode, using temp addr_reg. in EmitLoad()
406 addr_reg, g.TempImmediate(0)); in EmitLoad()
422 InstructionOperand addr_reg = g.TempRegister(); in EmitS128Load() local
424 addr_reg, g.UseRegister(index), g.UseRegister(base)); in EmitS128Load()
425 // Emit desired load opcode, using temp addr_reg. in EmitS128Load()
427 g.DefineAsRegister(node), addr_reg, g.TempImmediate(0), in EmitS128Load()
441 InstructionOperand addr_reg = g.TempRegister(); in VisitStoreLane() local
442 Emit(kRiscvAdd64, addr_reg, in VisitStoreLane()
461 InstructionOperand addr_reg = g.TempRegister(); VisitLoadLane() local
654 InstructionOperand addr_reg = g.TempRegister(); VisitStore() local
1812 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedLoad() local
1868 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedStore() local
2111 InstructionOperand addr_reg = g.TempRegister(); VisitWord32Compare() local
2134 InstructionOperand addr_reg = g.TempRegister(); VisitWord32Compare() local
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/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-selector-mips64.cc368 InstructionOperand addr_reg = g.TempRegister(); in EmitLoad() local
370 addr_reg, g.UseRegister(base), g.UseRegister(index)); in EmitLoad()
371 // Emit desired load opcode, using temp addr_reg. in EmitLoad()
374 addr_reg, g.TempImmediate(0)); in EmitLoad()
385 InstructionOperand addr_reg = g.TempRegister(); in EmitAddBeforeS128LoadStore() local
387 addr_reg, g.UseRegister(base), g.UseRegister(index)); in EmitAddBeforeS128LoadStore()
389 return addr_reg; in EmitAddBeforeS128LoadStore()
591 InstructionOperand addr_reg = g.TempRegister(); in VisitStore() local
592 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg, in VisitStore()
594 // Emit desired store opcode, using temp addr_reg in VisitStore()
1874 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedLoad() local
1930 InstructionOperand addr_reg = g.TempRegister(); VisitUnalignedStore() local
2197 InstructionOperand addr_reg = g.TempRegister(); VisitWord32Compare() local
2274 InstructionOperand addr_reg = g.TempRegister(); VisitWord32Compare() local
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/third_party/mesa3d/src/intel/common/
H A Dmi_builder.h1144 mi_store_address(struct mi_builder *b, struct mi_value addr_reg) in mi_store_address() argument
1148 assert(addr_reg.type == MI_VALUE_TYPE_REG64); in mi_store_address()
1154 srm.RegisterAddress = addr_reg.reg + (i * 4); in mi_store_address()
1162 mi_value_unref(b, addr_reg); in mi_store_address()
/third_party/mesa3d/src/mesa/program/
H A Dprog_to_nir.c62 nir_register *addr_reg; member
107 dest.dest.reg.reg = c->addr_reg; in ptn_get_dest()
184 index = nir_iadd(b, index, nir_load_reg(b, c->addr_reg)); in ptn_get_src()
985 c->addr_reg = reg; in setup_registers_and_variables()
/third_party/mesa3d/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi.c80 struct ureg_dst addr_reg[3]; member
1126 assert(addr_index < ARRAY_SIZE(c->addr_reg)); in ntt_reladdr()
1130 c->addr_reg[i] = ureg_writemask(ureg_DECL_address(c->ureg), in ntt_reladdr()
1137 ntt_UARL(c, c->addr_reg[addr_index], addr); in ntt_reladdr()
1139 ntt_ARL(c, c->addr_reg[addr_index], addr); in ntt_reladdr()
1140 return ureg_scalar(ureg_src(c->addr_reg[addr_index]), 0); in ntt_reladdr()
1728 nir_src src, int addr_reg) in ntt_ureg_src_indirect()
1734 return ureg_src_indirect(usrc, ntt_reladdr(c, ntt_get_src(c, src), addr_reg)); in ntt_ureg_src_indirect()
1727 ntt_ureg_src_indirect(struct ntt_compile *c, struct ureg_src usrc, nir_src src, int addr_reg) ntt_ureg_src_indirect() argument
H A Dtgsi_to_nir.c72 nir_register *addr_reg; member
253 c->addr_reg = nir_local_reg_create(b->impl); in ttn_emit_declaration()
254 c->addr_reg->num_components = 4; in ttn_emit_declaration()
582 src.reg.reg = c->addr_reg; in ttn_src_for_file_and_index()
820 dest.dest.reg.reg = c->addr_reg; in ttn_get_dest()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1993 unsigned addr_reg = instr->Rn();
1994 uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
2019 LoadStoreWriteBack(addr_reg, offset, addrmode);
2134 LoadStoreWriteBack(addr_reg, offset, addrmode);
2157 unsigned addr_reg = instr->Rn();
2160 uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
2182 LoadStoreWriteBack(addr_reg, offset, addrmode);
2303 LoadStoreWriteBack(addr_reg, offset, addrmode);
2344 uintptr_t Simulator::LoadStoreAddress(unsigned addr_reg, int64_t offset,
2347 uint64_t address = xreg(addr_reg, Reg31IsStackPointe
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H A Dsimulator-arm64.h1496 uintptr_t LoadStoreAddress(unsigned addr_reg, int64_t offset,
1498 void LoadStoreWriteBack(unsigned addr_reg, int64_t offset, AddrMode addrmode);
/third_party/node/deps/v8/src/compiler/backend/loong64/
H A Dinstruction-selector-loong64.cc1950 InstructionOperand addr_reg = g.TempRegister(); in VisitAtomicLoad() local
1952 addr_reg, g.UseRegister(index), g.UseRegister(base)); in VisitAtomicLoad()
1953 // Emit desired load opcode, using temp addr_reg. in VisitAtomicLoad()
1956 g.DefineAsRegister(node), addr_reg, g.TempImmediate(0)); in VisitAtomicLoad()
2019 InstructionOperand addr_reg = g.TempRegister(); in VisitAtomicStore() local
2021 addr_reg, g.UseRegister(index), g.UseRegister(base)); in VisitAtomicStore()
2022 // Emit desired store opcode, using temp addr_reg. in VisitAtomicStore()
2025 g.NoOutput(), addr_reg, g.TempImmediate(0), in VisitAtomicStore()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_shader.c1900 unsigned addr_reg; in fetch_gs_input() local
1901 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index); in fetch_gs_input()
1905 addr_reg, 0, in fetch_gs_input()
1946 int addr_reg; in fetch_gs_input() local
1949 addr_reg = get_address_file_reg(ctx, src->Indirect.Index); in fetch_gs_input()
1954 addr_reg, 0, in fetch_gs_input()
2070 unsigned addr_reg; in r600_get_byte_address() local
2073 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index); in r600_get_byte_address()
2075 sel = addr_reg; in r600_get_byte_address()
2104 int addr_reg; in r600_get_byte_address() local
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/third_party/node/deps/v8/src/wasm/baseline/arm64/
H A Dliftoff-assembler-arm64.h621 Register addr_reg, Register offset_reg, in CalculateActualAddress()
625 DCHECK_NE(addr_reg, no_reg); in CalculateActualAddress()
626 __ Add(result_reg, addr_reg, Operand(offset_reg)); in CalculateActualAddress()
620 CalculateActualAddress(LiftoffAssembler* lasm, Register addr_reg, Register offset_reg, uintptr_t offset_imm, Register result_reg) CalculateActualAddress() argument
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h105 Register addr_reg, Register offset_reg, in CalculateActualAddress()
110 return addr_reg; in CalculateActualAddress()
112 assm->mov(result_reg, addr_reg); in CalculateActualAddress()
119 assm->add(actual_addr_reg, addr_reg, Operand(offset_imm)); in CalculateActualAddress()
121 assm->add(actual_addr_reg, addr_reg, Operand(offset_reg)); in CalculateActualAddress()
103 CalculateActualAddress(LiftoffAssembler* assm, UseScratchRegisterScope* temps, Register addr_reg, Register offset_reg, uintptr_t offset_imm, Register result_reg = no_reg) CalculateActualAddress() argument
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc4227 unsigned addr_reg = instr->GetRn(); in Simulator() local
4229 uint64_t address = ReadXRegister(addr_reg, Reg31IsStackPointer); in Simulator()
4240 if ((addr_reg == 31) && ((address % 16) != 0)) { in Simulator()
4253 WriteXRegister(addr_reg, address, LogRegWrites, Reg31IsStackPointer); in Simulator()
5200 uintptr_t Simulator::AddressModeHelper(unsigned addr_reg, in Simulator() argument
5203 uint64_t address = ReadXRegister(addr_reg, Reg31IsStackPointer); in Simulator()
5205 if ((addr_reg == 31) && ((address % 16) != 0)) { in Simulator()
5218 WriteXRegister(addr_reg, address + offset, log_mode, Reg31IsStackPointer); in Simulator()
H A Dsimulator-aarch64.h3261 uintptr_t AddressModeHelper(unsigned addr_reg,
/third_party/node/deps/v8/src/wasm/baseline/riscv64/
H A Dliftoff-assembler-riscv64.h642 Register addr_reg, Register offset_reg, in CalculateActualAddress()
646 DCHECK_NE(addr_reg, no_reg); in CalculateActualAddress()
647 __ Add64(result_reg, addr_reg, Operand(offset_reg)); in CalculateActualAddress()
641 CalculateActualAddress(LiftoffAssembler* lasm, Register addr_reg, Register offset_reg, uintptr_t offset_imm, Register result_reg) CalculateActualAddress() argument
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c10167 const struct tgsi_full_src_register *addr_reg) in emit_uav_addr_offset()
10180 if (addr_reg) in emit_uav_addr_offset()
10181 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &addr_dst, addr_reg); in emit_uav_addr_offset()
10162 emit_uav_addr_offset(struct svga_shader_emitter_v10 *emit, enum tgsi_file_type resourceType, unsigned resourceIndex, unsigned resourceIndirect, unsigned resourceIndirectIndex, const struct tgsi_full_src_register *addr_reg) emit_uav_addr_offset() argument

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