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Searched refs:a6xx (Results 1 - 24 of 24) sorted by relevance

/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_compiler.c183 /* a6xx split the pipeline state into geometry and fragment state, in in ir3_compiler_create()
219 compiler->tess_use_shared = dev_info->a6xx.tess_use_shared; in ir3_compiler_create()
221 compiler->storage_16bit = dev_info->a6xx.storage_16bit; in ir3_compiler_create()
223 compiler->has_getfiberid = dev_info->a6xx.has_getfiberid; in ir3_compiler_create()
225 compiler->has_dp2acc = dev_info->a6xx.has_dp2acc; in ir3_compiler_create()
226 compiler->has_dp4acc = dev_info->a6xx.has_dp4acc; in ir3_compiler_create()
244 compiler->reg_size_vec4 = dev_info->a6xx.reg_size_vec4; in ir3_compiler_create()
297 compiler->nir_options.has_udot_4x8 = dev_info->a6xx.has_dp2acc; in ir3_compiler_create()
298 compiler->nir_options.has_sudot_4x8 = dev_info->a6xx.has_dp2acc; in ir3_compiler_create()
/third_party/mesa3d/src/freedreno/common/
H A Dfreedreno_devices.py107 """The a6xx generation has a lot more parameters, and is broken down
126 self.a6xx = Struct()
127 self.a6xx.magic = Struct()
130 setattr(self.a6xx.magic, name, val)
133 self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
134 self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
138 self.a6xx.has_cp_reg_write = True
139 self.a6xx.has_8bpp_ubwc = True
144 setattr(self.a6xx, name, val)
201 # a6xx ca
[all...]
H A Dfreedreno_dev_info.h81 /* newer a6xx allows using 16-bit descriptor for both 16-bit
107 /* The firmware on newer a6xx drops CP_REG_WRITE support as we
153 } a6xx; member
163 * Note that gpu-id should be considered deprecated. For newer a6xx, if
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_lrz.c155 if (cmd->device->physical_device->info->a6xx.lrz_track_quirk) { in tu6_write_lrz_reg()
199 cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking; in tu_lrz_init_state()
236 cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking; in tu_lrz_init_secondary()
307 if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking && in tu_lrz_begin_renderpass()
468 if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) { in tu_lrz_sysmem_begin()
502 if (!cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) in tu_disable_lrz()
521 !cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) in tu_lrz_clear_depth_image()
H A Dtu_nir_lower_multiview.c12 /* Some a6xx variants cannot support a non-contiguous multiview mask. Instead,
84 if (!dev->physical_device->info->a6xx.supports_multiview_mask) in tu_nir_lower_multiview()
94 dev->physical_device->info->a6xx.supports_multiview_mask ? 16 : 10; in tu_nir_lower_multiview()
H A Dtu_image.c291 if (!info->a6xx.has_8bpp_ubwc && in ubwc_possible()
335 if (!info->a6xx.has_z24uint_s8uint && samples > VK_SAMPLE_COUNT_1_BIT) in ubwc_possible()
561 device->physical_device->info->a6xx.enable_lrz_fast_clear && in tu_image_init()
564 if (has_lrz_fc || device->physical_device->info->a6xx.has_lrz_dir_tracking) { in tu_image_init()
568 if (device->physical_device->info->a6xx.has_lrz_dir_tracking) { in tu_image_init()
H A Dtu_device.c120 .KHR_16bit_storage = device->info->a6xx.storage_16bit, in get_device_extensions()
179 .EXT_sample_locations = device->info->a6xx.has_sample_locations, in get_device_extensions()
191 .EXT_filter_cubic = device->info->a6xx.has_tex_filter_cubic, in get_device_extensions()
224 .IMG_filter_cubic = device->info->a6xx.has_tex_filter_cubic, in get_device_extensions()
548 features->storageBuffer16BitAccess = pdevice->info->a6xx.storage_16bit; in tu_get_physical_device_features_1_1()
931 if (pdevice->info->a6xx.has_getfiberid) { in tu_get_physical_device_properties_1_1()
1065 pdevice->info->a6xx.has_dp2acc; in tu_get_physical_device_properties_1_3()
1069 pdevice->info->a6xx.has_dp2acc; in tu_get_physical_device_properties_1_3()
1083 pdevice->info->a6xx.has_dp2acc; in tu_get_physical_device_properties_1_3()
1087 pdevice->info->a6xx in tu_get_physical_device_properties_1_3()
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H A Dtu_shader.c67 .storage_16bit = dev->physical_device->info->a6xx.storage_16bit, in tu_spirv_to_nir()
256 if (dev->physical_device->info->a6xx.storage_16bit && in lower_ssbo_ubo_intrinsic()
H A Dtu_cmd_buffer.c99 (cmd_buffer->device->physical_device->info->a6xx.has_ccu_flush_bug && in tu6_emit_flushes()
352 bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write; in tu6_emit_render_cntl()
473 if (!device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk) in tu6_apply_depth_bounds_workaround()
834 phys_dev->info->a6xx.magic.TPL1_DBG_ECO_CNTL); in tu6_init_hw()
1027 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL)); in tu6_emit_binning_pass()
1030 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL)); in tu6_emit_binning_pass()
1158 if (!cmd->device->physical_device->info->a6xx.has_z24uint_s8uint) { in tu_emit_input_attachments()
1346 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL)); in tu6_tile_render_begin()
1349 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL)); in tu6_tile_render_begin()
3981 !cmd->device->physical_device->info->a6xx in tu_CmdBeginRendering()
[all...]
H A Dtu_pipeline.c564 MIN2(xs->instrlen, cs->device->physical_device->info->a6xx.instr_cache_size); in tu6_emit_xs()
693 if (cs->device->physical_device->info->a6xx.has_lpac) { in tu6_emit_cs_config()
714 if (cs->device->physical_device->info->a6xx.has_lpac) { in tu6_emit_cs_config()
1042 /* a6xx finds position/pointsize at the end */ in tu6_emit_vpc()
1754 if (builder->device->physical_device->info->a6xx.has_cp_reg_write) { in tu6_emit_program()
1767 builder->device->physical_device->info->a6xx.supports_multiview_mask) { in tu6_emit_program()
2301 ALIGN(per_fiber_size * dev->physical_device->info->a6xx.fibers_per_sp, 1 << 12); in calc_pvtmem_size()
3392 (builder->device->physical_device->info->a6xx.has_shading_rate ? 8 : 0) + in tu_pipeline_builder_parse_rasterization()
3416 if (builder->device->physical_device->info->a6xx.has_shading_rate) { in tu_pipeline_builder_parse_rasterization()
H A Dtu_descriptor_set.c61 if (dev->physical_device->info->a6xx.storage_16bit) { in descriptor_size()
897 bool storage_16bit = device->physical_device->info->a6xx.storage_16bit; in write_buffer_descriptor()
898 /* newer a6xx allows using 16-bit descriptor for both 16-bit and 32-bit in write_buffer_descriptor()
H A Dtu_clear_blit.c744 if (cmd->device->physical_device->info->a6xx.has_cp_reg_write) { in r3d_common()
2928 if (cmd->device->physical_device->info->a6xx.has_ccu_flush_bug) in tu_clear_sysmem_attachment()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_compute.c77 if (ctx->screen->info->a6xx.has_lpac) {
96 if (ctx->screen->info->a6xx.has_lpac) {
H A Dfd6_image.c72 ctx->screen->info->a6xx.storage_16bit ? PIPE_FORMAT_R16_UINT in fd6_ssbo_descriptor()
124 ctx->screen->info->a6xx.has_z24uint_s8uint); in fd6_emit_image_descriptor()
H A Dfd6_resource.c33 #include "a6xx.xml.h"
52 return info->a6xx.has_z24uint_s8uint; in ok_ubwc_format()
91 return info->a6xx.has_8bpp_ubwc; in ok_ubwc_format()
H A Dfd6_gmem.c186 // XXX a6xx seems to use a different buffer here.. not sure in emit_zs()
333 batch->ctx->screen->info->a6xx.has_z24uint_s8uint); in patch_fb_read_sysmem()
381 if (screen->info->a6xx.has_cp_reg_write) { in update_render_cntl()
711 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
714 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
764 .concurrent_resolve = screen->info->a6xx.concurrent_resolve));
832 .concurrent_resolve = screen->info->a6xx.concurrent_resolve));
867 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
870 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
H A Dfd6_rasterizer.c96 if (ctx->screen->info->a6xx.has_shading_rate) { in __fd6_setup_rasterizer_stateobj()
H A Dfd6_blitter.c416 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit); in emit_blit_buffer()
511 OUT_RING(ring, batch->ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
689 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit); in emit_blit_texture()
817 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit); in fd6_clear_surface()
1072 if (!ctx->screen->info->a6xx.has_z24uint_s8uint) {
H A Dfd6_program.c105 uint32_t fibers_per_sp = ctx->screen->info->a6xx.fibers_per_sp; in fd6_emit_shader()
146 MIN2(so->instrlen, ctx->screen->info->a6xx.instr_cache_size); in fd6_emit_shader()
166 if (ctx->screen->info->a6xx.tess_use_shared) in setup_stream_out_disable()
178 if (ctx->screen->info->a6xx.tess_use_shared) { in setup_stream_out_disable()
243 if (ctx->screen->info->a6xx.tess_use_shared) in setup_stream_out()
279 if (ctx->screen->info->a6xx.tess_use_shared) { in setup_stream_out()
720 if (ctx->screen->info->a6xx.tess_use_shared) {
H A Dfd6_texture.c267 ctx->screen->info->a6xx.has_z24uint_s8uint); in fd6_sampler_view_update()
H A Dfd6_draw.c435 OUT_RING(ring, screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
H A Dfd6_emit.c53 * the same as a6xx then move this somewhere common ;-)
87 const bool has_z24uint_s8uint = screen->info->a6xx.has_z24uint_s8uint; in setup_border_colors()
1264 WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL); in fd6_emit_restore()
/third_party/mesa3d/src/freedreno/computerator/
H A Da6xx.c30 #include "a6xx.xml.h"
162 if (a6xx_backend->info->a6xx.has_lpac) { in cs_program_emit()
181 if (a6xx_backend->info->a6xx.has_lpac) { in cs_program_emit()
201 MIN2(v->instrlen, a6xx_backend->info->a6xx.instr_cache_size); in cs_program_emit()
213 ALIGN(per_fiber_size * a6xx_backend->info->a6xx.fibers_per_sp, 1 << 12); in cs_program_emit()
/third_party/mesa3d/src/freedreno/.gitlab-ci/reference/
H A Dafuc_test.asm0 ; a6xx microcode

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