Searched refs:ZeroExtend (Results 1 - 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/spirv-headers/include/spirv/unified1/ |
| H A D | spirv.cs | 351 ZeroExtend = 13, enumerator
375 ZeroExtend = 0x00002000, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Headers/include/spirv/unified1/ |
| H A D | spirv.cs | 351 ZeroExtend = 13, enumerator
375 ZeroExtend = 0x00002000, enumerator
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| /third_party/spirv-headers/include/spirv/unified1/ |
| H A D | spirv.cs | 389 ZeroExtend = 13, enumerator
414 ZeroExtend = 0x00002000, enumerator
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| /third_party/spirv-tools/source/val/ |
| H A D | validate_image.cpp | 68 case spv::ImageOperandsMask::ZeroExtend: in CheckAllImageOperandsHandled()
259 // NonPrivate, Volatile, SignExtend, ZeroExtend take no operand words. in ValidateImageOperands()
264 spv::ImageOperandsMask::ZeroExtend | in ValidateImageOperands()
626 if (mask & uint32_t(spv::ImageOperandsMask::ZeroExtend)) { in ValidateImageOperands()
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| /third_party/node/deps/v8/src/codegen/ppc/ |
| H A D | macro-assembler-ppc.h | 321 void ZeroExtend(Register dst, Register value) { in ZeroExtend() function in v8::internal::TurboAssembler
344 ZeroExtend<_type>(dst, value); in ExtendValue()
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 627 register_.Insert(byte_index, ZeroExtend(byte, bit_offset, psize, value)); in SetActive()
679 uint8_t ZeroExtend(uint8_t byte, int index, int psize, bool value) { in ZeroExtend() function in vixl::aarch64::LogicPRegister
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5777 auto ZeroExtend = N->use_begin(); in ExpandBITCAST()
5778 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND || in ExpandBITCAST()
5779 ZeroExtend->getValueType(0) != MVT::i32) in ExpandBITCAST()
5782 auto Copy = ZeroExtend->use_begin(); in ExpandBITCAST()
5786 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt); in ExpandBITCAST()
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