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Searched refs:ZERO_EXTEND (Results 1 - 25 of 46) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp183 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
185 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
187 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
189 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
191 {ISD::ZERO_EXTEND, MVT::i64, MVT::i16, 1}, in getCastInstrCost()
193 {ISD::ZERO_EXTEND, MVT::i64, MVT::i8, 1}, in getCastInstrCost()
201 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
203 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
205 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
220 { ISD::ZERO_EXTEND, MV in getCastInstrCost()
[all...]
H A DARMSelectionDAGInfo.cpp93 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitSpecializedLibcall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1283 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, in getCastInstrCost() member in ISD
1294 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, in getCastInstrCost() member in ISD
1295 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, in getCastInstrCost() member in ISD
1296 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, in getCastInstrCost() member in ISD
1297 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost() member in ISD
1298 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, in getCastInstrCost() member in ISD
1299 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, in getCastInstrCost() member in ISD
1347 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
1349 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
1351 { ISD::ZERO_EXTEND, MV in getCastInstrCost()
[all...]
H A DX86ISelLowering.cpp808 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); in X86TargetLowering()
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1218 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1236 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in X86TargetLowering()
1411 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in X86TargetLowering()
1514 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1515 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1523 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i8, Custom); in X86TargetLowering()
1760 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom); in X86TargetLowering()
1773 setOperationAction(ISD::ZERO_EXTEND, MV in X86TargetLowering()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
313 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
315 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
317 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
319 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
321 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
323 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h528 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
529 ZERO_EXTEND, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1135 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1560 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1667 case ISD::ZERO_EXTEND: in combine()
2013 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2148 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADDLike()
2151 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not); in visitADDLike()
2369 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization. in getAsCarry()
2371 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2475 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADDLikeCommutative()
2871 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND) in combineCarryDiamond()
[all...]
H A DLegalizeDAG.cpp1544 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
2534 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2543 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2837 case ISD::ZERO_EXTEND:
3342 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3384 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3390 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3509 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
4244 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4269 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, d
[all...]
H A DTargetLowering.cpp534 /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1677 case ISD::ZERO_EXTEND: in SimplifyDemandedBits()
1752 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
1913 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); in SimplifyDemandedBits()
2604 case ISD::ZERO_EXTEND: in SimplifyDemandedVectorElts()
2609 if (Op.getOpcode() == ISD::ZERO_EXTEND) { in SimplifyDemandedVectorElts()
3222 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
3284 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && in SimplifySetCC()
3361 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. in SimplifySetCC()
3362 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
[all...]
H A DLegalizeIntegerTypes.cpp116 case ISD::ZERO_EXTEND: in PromoteIntegerResult()
439 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
580 if (N->getOpcode() == ISD::ZERO_EXTEND) in PromoteIntRes_INT_EXTEND()
1048 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc); in PromoteIntRes_TRUNCATE()
1207 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); in PromoteIntRes_VAARG()
1209 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); in PromoteIntRes_VAARG()
1287 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; in PromoteIntegerOperand()
1833 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
3562 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow), in ExpandIntRes_XMULO()
3563 DAG.getNode(ISD::ZERO_EXTEND, d in ExpandIntRes_XMULO()
[all...]
H A DLegalizeVectorTypes.cpp103 case ISD::ZERO_EXTEND: in ScalarizeVectorResult()
397 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
568 case ISD::ZERO_EXTEND: in ScalarizeVectorOperand()
902 case ISD::ZERO_EXTEND: in SplitVectorResult()
1971 case ISD::ZERO_EXTEND: in SplitVectorOperand()
2800 case ISD::ZERO_EXTEND: in WidenVectorResult()
3254 if (Opcode == ISD::ZERO_EXTEND) in WidenVecRes_Convert()
3382 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val); in WidenVecRes_EXTEND_VECTOR_INREG()
4205 case ISD::ZERO_EXTEND: in WidenVectorOperand()
4318 case ISD::ZERO_EXTEND in WidenVecOp_EXTEND()
[all...]
H A DLegalizeTypes.cpp971 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); in JoinIntegers()
H A DSelectionDAGDumper.cpp320 case ISD::ZERO_EXTEND: return "zero_extend"; in getOperationName()
H A DLegalizeVectorOps.cpp404 case ISD::ZERO_EXTEND: in LegalizeOp()
634 ? ISD::ZERO_EXTEND in PromoteINT_TO_FP()
H A DSelectionDAG.cpp341 return ISD::ZERO_EXTEND;
1156 getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
3084 case ISD::ZERO_EXTEND: {
4397 case ISD::ZERO_EXTEND:
4537 case ISD::ZERO_EXTEND:
4608 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
4614 case ISD::ZERO_EXTEND:
4616 "Invalid ZERO_EXTEND!");
4618 "ZERO_EXTEND result type type should be vector iff the operand "
4627 if (OpOpcode == ISD::ZERO_EXTEND) // (zex
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp103 setOperationAction(ISD::ZERO_EXTEND, T, Custom); in initializeHVXLowering()
136 setOperationAction(ISD::ZERO_EXTEND, T, Custom); in initializeHVXLowering()
1215 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), ResTy, InpV); in LowerHvxAnyExt()
1554 case ISD::ZERO_EXTEND: in LowerHvxOperation()
1572 case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG); in LowerHvxOperation()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp709 if (Index.getOpcode() == ISD::ZERO_EXTEND) in selectBDVAddr12Only()
850 case ISD::ZERO_EXTEND: in expandRxSBG()
1525 case ISD::ZERO_EXTEND: in Select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1169 setTargetDAGCombine(ISD::ZERO_EXTEND); in PPCTargetLowering()
5730 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in LowerCall_32SVR4()
6063 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
6626 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
6691 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg); in LowerCall_Darwin()
7133 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_AIX()
7259 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
7490 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()), in LowerSTORE()
8181 SINT.getOpcode() == ISD::ZERO_EXTEND)) && in LowerINT_TO_FP()
8207 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND in LowerINT_TO_FP()
[all...]
H A DPPCISelDAGToDAG.cpp1344 case ISD::ZERO_EXTEND: { in getValueBits()
1723 // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
2522 case ISD::ZERO_EXTEND: in Select()
2547 assert((N->getOpcode() == ISD::ZERO_EXTEND || in tryEXTEND()
2555 N->getOpcode() == ISD::ZERO_EXTEND) in tryEXTEND()
2780 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND); in zeroExtendInputIfNeeded()
3581 CompareUse->getOpcode() != ISD::ZERO_EXTEND && in allUsesExtend()
3651 case ISD::ZERO_EXTEND: in tryIntCompareInGPR()
4258 (TrueResVal == -1 && FalseRes.getOpcode() != ISD::ZERO_EXTEND) || in mayUseP9Setb()
5523 if (N->getOpcode() != ISD::ZERO_EXTEND in foldBoolExts()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
809 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
1151 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1202 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
2920 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2921 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp583 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand); in SITargetLowering()
588 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand); in SITargetLowering()
739 setTargetDAGCombine(ISD::ZERO_EXTEND); in SITargetLowering()
2336 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
2803 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
4222 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in lowerICMPIntrinsic()
5014 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5022 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
6779 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData); in handleD16VData()
7264 return DAG.getNode(ISD::ZERO_EXTEND, S in getLoadExtOrTrunc()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1524 : ISD::ZERO_EXTEND, in LowerCall()
2419 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
2613 : ISD::ZERO_EXTEND; in LowerFormalArguments()
2701 : ISD::ZERO_EXTEND, in LowerReturn()
4528 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in PerformANDCombine()
4592 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) { in IsMulWideOperandDemotable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp340 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1482 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1621 case ZExt: return ISD::ZERO_EXTEND; in InstructionOpcodeToISD()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
1369 case ISD::ZERO_EXTEND: { in isConditionalZeroOrAllOnes()

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