| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAtomicOptimizer.cpp | 126 case AtomicRMWInst::Xor: in visitAtomicRMWInst()
191 Op = AtomicRMWInst::Xor; in visitIntrinsicInst()
261 case AtomicRMWInst::Xor: in buildNonAtomicBinOp()
262 return B.CreateBinOp(Instruction::Xor, LHS, RHS); in buildNonAtomicBinOp()
394 case AtomicRMWInst::Xor: in getIdentityValueForAtomicOp()
542 case AtomicRMWInst::Xor: in optimizeAtomic()
636 case AtomicRMWInst::Xor: in optimizeAtomic()
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| H A D | SILowerControlFlow.cpp | 232 MachineInstr *Xor = nullptr; in emitIf() local
234 Xor = in emitIf()
238 setImpSCCDefDead(*Xor, ImpDefSCC.isDead()); in emitIf()
264 LIS->InsertMachineInstrInMaps(*Xor); in emitIf()
320 MachineInstr *Xor = in emitElse() local
340 LIS->InsertMachineInstrInMaps(*Xor); in emitElse()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | TruncInstCombine.cpp | 55 case Instruction::Xor: in getRelevantOperands()
117 case Instruction::Xor: { in buildTruncExpressionDag()
348 case Instruction::Xor: { in ReduceExpressionDag()
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| /third_party/skia/src/opts/ |
| H A D | SkXfermode_opts.h | 45 XFERMODE(Xor) { return (s * d.alphas().inv() + d * s.alphas().inv()).div255(); }
123 CASE(Xor);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 176 return Opcode == And || Opcode == Or || Opcode == Xor; in isBitwiseLogicOp()
483 /// In LLVM, the Add, Mul, And, Or, and Xor operators are associative.
487 return Opcode == And || Opcode == Or || Opcode == Xor || in isAssociative()
503 case And: case Or: case Xor: in isCommutative()
528 /// In LLVM, the Xor operator is nilpotent.
532 return Opcode == Xor; in isNilpotent()
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| /third_party/skia/docs/examples/ |
| H A D | Xor.cpp | 5 REG_FIDDLE(Xor, 256, 256, false, 0) { in REG_FIDDLE()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 987 case Instruction::Xor: in isPromotableTo()
1239 case Instruction::Xor: in commutesWithShift()
1274 case Instruction::Xor: in keepsHighBitsZero()
1577 case Instruction::Xor: in hasZeroSignBit()
1599 case Instruction::Xor: in setupPreSimplifier()
1612 if (I->getOpcode() != Instruction::Xor) in setupPreSimplifier()
1695 case Instruction::Xor: in setupPreSimplifier()
1713 case Instruction::Xor: in setupPreSimplifier()
1740 Instruction *Xor = dyn_cast<Instruction>(I->getOperand(0)); in setupPostSimplifier()
1742 if (!Xor || !C in setupPostSimplifier()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 55 case Instruction::Xor: in getIntImmCostInst()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| H A D | LowerExpectIntrinsic.cpp | 133 if (!BinOp || BinOp->getOpcode() != Instruction::Xor) in handlePhiDef()
149 case Instruction::Xor: in handlePhiDef()
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| H A D | LowerAtomic.cpp | 71 case AtomicRMWInst::Xor: in LowerAtomicRMWInst()
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| H A D | SpeculativeExecution.cpp | 225 case Instruction::Xor: in ComputeSpeculationCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTDC.cpp | 105 LI->getOpcode() == Instruction::Xor)) { in converted()
303 case Instruction::Xor: in convertLogicOp()
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| H A D | SystemZTargetTransformInfo.cpp | 127 case Instruction::Xor: in getIntImmCostInst()
471 if (Opcode == Instruction::Xor) { in getArithmeticInstrCost()
477 I->getOpcode() == Instruction::Xor)) in getArithmeticInstrCost()
484 if (I->hasOneUse() && I->getOpcode() == Instruction::Xor) in getArithmeticInstrCost()
494 if (Opcode == Instruction::Xor && ScalarBits == 1) { in getArithmeticInstrCost()
965 case Instruction::Xor: in isFoldableLoad()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAtomicRMW.cpp | 42 case AtomicRMWInst::Xor: in isIdempotentRMW()
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| H A D | InstCombineAndOrXor.cpp | 829 APInt Xor = *C1 ^ *C2; in foldAndOrOfEqualityCmpsWithConstants() local
830 if (Xor.isPowerOf2()) { in foldAndOrOfEqualityCmpsWithConstants()
837 Value *Or = Builder.CreateOr(X, ConstantInt::get(X->getType(), Xor)); in foldAndOrOfEqualityCmpsWithConstants()
1575 if (LogicOpc == Instruction::Xor) in foldCastedBitwiseLogic()
1740 if (Instruction *Xor = foldAndToXor(I, Builder)) in visitAnd()
1741 return Xor; in visitAnd()
1819 case Instruction::Xor: in visitAnd()
2465 if (Instruction *Xor = foldOrToXor(I, Builder)) in visitOr()
2466 return Xor; in visitOr()
2629 B->getOpcode() == Instruction::Xor)) { in visitOr()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | ExpandReductions.cpp | 46 return Instruction::Xor; in getOpcode()
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| H A D | AtomicExpandPass.cpp | 319 (Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor || in runOnFunction()
542 case AtomicRMWInst::Xor: in performAtomicOp()
702 case AtomicRMWInst::Xor: in performMaskedAtomicOp()
704 llvm_unreachable("Or/Xor/And handled by widenPartwordAtomicRMW"); in performMaskedAtomicOp()
780 assert((Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor || in widenPartwordAtomicRMW()
1327 case AtomicRMWInst::Xor: in isIdempotentRMW()
1554 case AtomicRMWInst::Xor: in GetRMWLibcall()
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| /third_party/skia/third_party/externals/dawn/src/tests/unittests/ |
| H A D | ITypBitsetTests.cpp | 168 TEST_F(ITypBitsetTest, Xor) { in TEST_F()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/FuzzMutate/ |
| H A D | Operations.cpp | 31 Ops.push_back(binOpDescriptor(1, Instruction::Xor)); in describeFuzzerIntOps()
109 case Instruction::Xor: in binOpDescriptor()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| H A D | MCExpr.h | 448 Xor ///< Bitwise exclusive or. enumerator
559 return create(Xor, LHS, RHS, Ctx); in createXor()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/pnacl-llvm/ |
| H A D | NaClBitcodeDecoders.cpp | 112 LLVMOpcode = Instruction::Xor; in DecodeBinaryOpcode()
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| /third_party/typescript/tests/baselines/reference/ |
| H A D | parserRealSource3.js | 56 Xor,
177 NodeType[NodeType["Xor"] = 46] = "Xor";
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | code-generator-riscv64.cc | 1098 __ Xor(i.OutputRegister(), i.InputOrZeroRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1101 __ Xor(i.OutputRegister(), i.InputOrZeroRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1911 ATOMIC_BINOP_CASE(Xor, Xor, Xor) in AssembleArchInstruction()
3638 __ Xor(result, kScratchReg, kScratchReg2); in AssembleArchBoolean()
3640 __ Xor(result, result, 1); in AssembleArchBoolean()
3674 __ Xor(result, left, right); in AssembleArchBoolean()
3677 __ Xor(result, left, kScratchReg); in AssembleArchBoolean()
3686 __ Xor(resul in AssembleArchBoolean()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerX8632.h | 739 void Xor(Type Ty, GPRRegister dst, GPRRegister src);
740 void Xor(Type Ty, GPRRegister dst, const AsmAddress &address);
741 void Xor(Type Ty, GPRRegister dst, const Immediate &imm);
742 void Xor(Type Ty, const AsmAddress &address, GPRRegister reg);
743 void Xor(Type Ty, const AsmAddress &address, const Immediate &imm);
917 // of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
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| H A D | IceAssemblerX8664.h | 734 void Xor(Type Ty, GPRRegister dst, GPRRegister src);
735 void Xor(Type Ty, GPRRegister dst, const AsmAddress &address);
736 void Xor(Type Ty, GPRRegister dst, const Immediate &imm);
737 void Xor(Type Ty, const AsmAddress &address, GPRRegister reg);
738 void Xor(Type Ty, const AsmAddress &address, const Immediate &imm);
913 // of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
|