Searched refs:XMM0 (Results 1 - 12 of 12) sorted by relevance
| /third_party/mesa3d/src/mesa/x86/ |
| H A D | common_x86_asm.S | 167 XORPS ( XMM0, XMM0 )
196 XORPS ( XMM0, XMM0 )
205 DIVPS ( XMM0, XMM1 )
|
| H A D | assyntax.h | 224 #define XMM0 %xmm0 macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 321 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem64_RC128()
324 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem128_RC128()
330 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem256_RC128()
337 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem64_RC128X()
340 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem128_RC128X()
346 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem256_RC128X()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.cpp | 80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
|
| H A D | X86CallLowering.cpp | 165 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
|
| H A D | X86RegisterInfo.cpp | 600 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
|
| H A D | X86FastISel.cpp | 2236 // uses XMM0 as the selection register. That may need just as many in X86FastEmitSSESelect()
3125 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerArguments()
3462 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerCall()
|
| H A D | X86ISelLowering.cpp | 2723 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 in LowerReturn()
2727 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
3336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in get64BitArgumentXMMs()
4008 case X86::XMM0: ShadowReg = X86::RCX; break;
4066 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
22091 // uses XMM0 as the selection register. That may need just as many
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 219 ENTRY(XMM0) \
|
| H A D | X86Disassembler.cpp | 812 // the operand is an XMM operand, for example, an operand would be XMM0 instead
1941 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 134 {codeview::RegisterId::XMM0, X86::XMM0}, in initLLVMToSEHAndCVRegMapping()
|
| H A D | X86InstComments.cpp | 207 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31) in getVectorRegSize()
|
Completed in 49 milliseconds