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Searched refs:X8 (Results 1 - 25 of 25) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/gfx10/
H A Dgfx10SwizzlePattern.h3814 {Y4^Z4^X8, Z3^X4^Y8, Z2^Y5^X7, Z1^X5^Y7, }, // 26
3815 {Y3^Z4^X8, Z3^X4^Y7, Z2^Y4^X7, Z1^X5^Y6, }, // 27
3819 {Y4^Z5^X9, X4^Z4^Y9, Z3^Y5^X8, Z2^X5^Y8, }, // 31
3820 {Y3^Z5^X9, X4^Z4^Y8, Z3^Y4^X8, Z2^X5^Y7, }, // 32
3821 {Y3^Z5^X8, X3^Z4^Y8, Z3^Y4^X7, Z2^X4^Y7, }, // 33
3822 {Y2^Z5^X8, X3^Z4^Y7, Y3^Z3^X7, Z2^X4^Y6, }, // 34
3865 {X3^Y3^Z5, X4^Y4^Z4, Z3^Y5^X8, Z2^X5^Y8, }, // 77
3866 {X3^Y3^Z4, Z3^X4^Y4, Z2^Y5^X8, Z1^X5^Y8, }, // 78
3867 {X3^Y3^Z3, Z2^X4^Y4, Z1^Y5^X8, Z0^X5^Y8, }, // 79
3877 {Z2^X3^Y3, Z1^X4^Y4, Z0^Y5^X8, Y
[all...]
/third_party/mesa3d/src/amd/addrlib/src/gfx11/
H A Dgfx11SwizzlePattern.h1877 {Y4^X8, X4^Y8, Z2^Y5^X7, Z1^X5^Y7, }, // 66
1878 {Y3^X8, X4^Y7, Z2^Y4^X7, Z1^X5^Y6, }, // 67
1882 {Y4^X8, Z3^X4^Y8, Z2^Y5^X7, Z1^X5^Y7, }, // 71
1883 {Y3^X8, Z3^X4^Y7, Z2^Y4^X7, Z1^X5^Y6, }, // 72
1887 {Y4^X9, X4^Y9, Z3^Y5^X8, Z2^X5^Y8, }, // 76
1888 {Y3^X9, X4^Y8, Z3^Y4^X8, Z2^X5^Y7, }, // 77
1889 {Y3^X8, X3^Y8, Z3^Y4^X7, Z2^X4^Y7, }, // 78
1890 {Y2^X8, X3^Y7, Y3^Z3^X7, Z2^X4^Y6, }, // 79
1892 {Y4^Z4^X8, Z3^X4^Y8, Z2^Y5^X7, Z1^X5^Y7, }, // 81
1893 {Y3^Z4^X8, Z
[all...]
/third_party/typescript/tests/baselines/reference/
H A DmissingTypeArguments1.js39 class X8<T> {
42 var a8: X8<number>;
105 var X8 = /** @class */ (function () {
106 function X8() {
108 return X8;
H A DinferTypesWithExtends1.js74 type X8<T> =
79 type X8_T1 = X8<{ a: "a", b: "b" }>; // ["string", "a" | "b"]
80 type X8_T2 = X8<{ a: 1, b: 2 }>; // ["number", 1 | 2]
81 type X8_T3 = X8<{ a: object, b: object }>; // never
82 type X8_T4 = X8<{ a: "a", b: 1 }>; // never
216 type X8<T> = T extends {
223 type X8_T1 = X8<{
227 type X8_T2 = X8<{
231 type X8_T3 = X8<{
235 type X8_T4 = X8<{
[all...]
/third_party/ffmpeg/libavcodec/x86/
H A Dfdct.c59 #define X8(x) x,x,x,x,x,x,x,x macro
63 X8(13036), // tg * (2<<16) + 0.5
64 X8(27146), // tg * (2<<16) + 0.5
65 X8(-21746) // tg * (2<<16) + 0.5
69 X8(23170) //cos * (2<<15) + 0.5
72 DECLARE_ALIGNED(16, static const int16_t, fdct_one_corr)[8] = { X8(1) };
/third_party/ffmpeg/libavutil/x86/
H A Dasm.h137 # define FE_8(P,X,X1,X2,X3,X4,X5,X6,X7,X8) P(X), FE_7(P,X1,X2,X3,X4,X5,X6,X7,X8)
138 # define FE_9(P,X,X1,X2,X3,X4,X5,X6,X7,X8,X9) P(X), FE_8(P,X1,X2,X3,X4,X5,X6,X7,X8,X9)
/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha1-c64xplus.pl40 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27");
142 || LDW *${XPA}[7],$X8
168 || XOR $X8,$X13,$TX1
169 || LDW *${XPA}[7],$X8
199 || XOR $X8,$X13,$TX1
200 || LDW *${XPA}[7],$X8
236 || XOR $X8,$X13,$TX1
237 || LDW *${XPA}[7],$X8
276 || XOR $X8,$X13,$TX1
277 || LDW *${XPA}[7],$X8
[all...]
/third_party/openssl/crypto/sha/asm/
H A Dsha1-c64xplus.pl40 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27");
142 || LDW *${XPA}[7],$X8
168 || XOR $X8,$X13,$TX1
169 || LDW *${XPA}[7],$X8
199 || XOR $X8,$X13,$TX1
200 || LDW *${XPA}[7],$X8
236 || XOR $X8,$X13,$TX1
237 || LDW *${XPA}[7],$X8
276 || XOR $X8,$X13,$TX1
277 || LDW *${XPA}[7],$X8
[all...]
/third_party/ffmpeg/libswscale/aarch64/
H A Dswscale.c35 SCALE_FUNCS(X8, opt)
54 ASSIGN_SCALE_FUNC2(hscalefn, X8, opt); \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp84 markSuperRegs(Reserved, RISCV::X8); // fp in getReservedRegs()
152 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; in getFrameRegister()
H A DRISCVFrameLowering.cpp103 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } in getFPReg()
361 SavedRegs.set(RISCV::X8); in determineCalleeSaves()
H A DRISCVISelLowering.cpp2596 .Cases("{s0}", "{fp}", RISCV::X8) in getRegForInlineAsmConstraint()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ToolDrivers/llvm-dlltool/
H A DDlltoolDriver.cpp42 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \
44 X9, X8, OPT_##GROUP, OPT_##ALIAS, X7, X12},
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ToolDrivers/llvm-lib/
H A DLibDriver.cpp48 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \
50 X9, X8, OPT_##GROUP, OPT_##ALIAS, X7, X12},
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h39 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
79 case AArch64::W8: return AArch64::X8; in getXRegFromWReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp402 // Conservatively forward X8, since it might be used for an aggregate in handleMustTailForwardedRegisters()
404 if (!CCInfo.isAllocated(AArch64::X8)) { in handleMustTailForwardedRegisters()
405 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()
406 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64)); in handleMustTailForwardedRegisters()
H A DAArch64ISelLowering.cpp3533 // Conservatively forward X8, since it might be used for aggregate return. in LowerFormalArguments()
3534 if (!CCInfo.isAllocated(AArch64::X8)) { in LowerFormalArguments()
3535 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in LowerFormalArguments()
3536 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64)); in LowerFormalArguments()
/third_party/ffmpeg/libswscale/x86/
H A Dscale.asm229 %else ; %4 == X || %4 == X8
368 SCALE_FUNC %1, %2, X, X8, 7, %3
H A Dswscale.c262 SCALE_FUNCS(X8, opt)
529 else ASSIGN_SCALE_FUNC2(hscalefn, X8, opt1, opt2); \ in ff_sws_init_swscale_x86()
/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_format.c72 MAP_FORMAT2(BITS ## X8, TYPE, BITS ## A8, TYPE) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp146 Register Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrlib2.h180 const UINT_64 X8 = InitBit(0, 8); member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp105 {codeview::RegisterId::ARM64_X8, AArch64::X8}, in initLLVMToCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp419 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3765 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerFormalArguments_64SVR4()
4180 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerFormalArguments_Darwin()
4603 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in needStackSlotPassParameters()
5863 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerCall_64SVR4()
6595 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerCall_Darwin()
6887 PPC::X7, PPC::X8, PPC::X9, PPC::X10}; in CC_AIX()

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