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/third_party/node/deps/v8/src/codegen/x64/
H A Dfma-instr.h23 V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
24 V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \
25 V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \
26 V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \
27 V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \
28 V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \
29 V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \
30 V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \
31 V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \
32 V(vfnmsub132ss, LIG, 66, 0F, 38, W0,
[all...]
/third_party/node/deps/v8/src/codegen/ia32/
H A Dfma-instr.h23 V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
24 V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \
25 V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \
26 V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \
27 V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \
28 V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \
29 V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \
30 V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \
31 V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \
32 V(vfnmsub132ss, LIG, 66, 0F, 38, W0,
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
325 return rr0(eIMM(im(1), W0), Outputs);
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
347 uint16_t RW = W0;
356 uint16_t RW = W0;
372 assert(W0
[all...]
H A DHexagonVectorPrint.cpp75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
185 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
186 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction()
187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
H A DHexagonISelLoweringHVX.cpp553 SDValue W0 = isUndef(PredV) in createHvxPrefixPred() local
556 Words[IdxW].push_back(Hi32(W0)); in createHvxPrefixPred()
557 Words[IdxW].push_back(Lo32(W0)); in createHvxPrefixPred()
802 SDValue W0 = extractHvxElementReg(WordVec, W0Idx, dl, MVT::i32, DAG); in extractHvxSubvectorReg() local
804 return DAG.getBitcast(ResTy, W0); in extractHvxSubvectorReg()
808 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg()
868 SDValue W0 = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32, {ShuffV, Zero}); in extractHvxSubvectorPred() local
871 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
H A DHexagonRegisterInfo.cpp74 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0 in getCallerSavedRegs()
/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha512-armv8.pl364 my ($W0,$W1)=("v16.4s","v17.4s");
382 ld1.32 {$W0},[$Ktbl],#16
393 add.i32 $W0,$W0,@MSG[0]
396 sha256h $ABCD,$EFGH,$W0
397 sha256h2 $EFGH,$abcd,$W0
400 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
404 add.i32 $W0,$W0,
[all...]
H A Dsha256-armv4.pl608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
634 vld1.32 {$W0},[$Ktbl]!
646 vadd.i32 $W0,$W0,@MSG[0]
649 sha256h $ABCD,$EFGH,$W0
650 sha256h2 $EFGH,$abcd,$W0
653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
657 vadd.i32 $W0,$W0,
[all...]
H A Dsha1-armv8.pl248 my ($W0,$W1)=("v20.4s","v21.4s");
272 add.i32 $W0,@Kxx[0],@MSG[0]
279 sha1c $ABCD,$E,$W0 // 0
280 add.i32 $W0,@Kxx[$j],@MSG[2]
294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
303 sha1p $ABCD,$E0,$W0
H A Dsha1-armv4-large.pl624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
658 vadd.i32 $W0,@Kxx[0],@MSG[0]
666 sha1c $ABCD,$E,$W0
667 vadd.i32 $W0,@Kxx[$j],@MSG[2]
681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
690 sha1p $ABCD,$E0,$W0
/third_party/openssl/crypto/sha/asm/
H A Dsha512-armv8.pl369 my ($W0,$W1)=("v16.4s","v17.4s");
388 ld1.32 {$W0},[$Ktbl],#16
399 add.i32 $W0,$W0,@MSG[0]
402 sha256h $ABCD,$EFGH,$W0
403 sha256h2 $EFGH,$abcd,$W0
406 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
410 add.i32 $W0,$W0,
[all...]
H A Dsha256-armv4.pl608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
634 vld1.32 {$W0},[$Ktbl]!
646 vadd.i32 $W0,$W0,@MSG[0]
649 sha256h $ABCD,$EFGH,$W0
650 sha256h2 $EFGH,$abcd,$W0
653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
657 vadd.i32 $W0,$W0,
[all...]
H A Dsha1-armv8.pl248 my ($W0,$W1)=("v20.4s","v21.4s");
273 add.i32 $W0,@Kxx[0],@MSG[0]
280 sha1c $ABCD,$E,$W0 // 0
281 add.i32 $W0,@Kxx[$j],@MSG[2]
295 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
304 sha1p $ABCD,$E0,$W0
H A Dsha1-armv4-large.pl624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
658 vadd.i32 $W0,@Kxx[0],@MSG[0]
666 sha1c $ABCD,$E,$W0
667 vadd.i32 $W0,@Kxx[$j],@MSG[2]
681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
690 sha1p $ABCD,$E0,$W0
/third_party/ffmpeg/libavcodec/mips/
H A Dwmv2dsp_mmi.c28 #define W0 2048 macro
43 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row_mmi()
47 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row_mmi()
73 a0 = (W0 * b[ 0] + W0 * b[32] ) >> 3; in wmv2_idct_col_mmi()
77 a4 = (W0 * b[ 0] - W0 * b[32] ) >> 3; in wmv2_idct_col_mmi()
/third_party/ffmpeg/libavcodec/
H A Dwmv2dsp.c27 #define W0 2048 macro
48 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row()
49 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row()
78 a0 = (W0 * b[8 * 0] + W0 * b[8 * 4] ) >> 3; in wmv2_idct_col()
79 a4 = (W0 * b[8 * 0] - W0 * b[8 * 4] ) >> 3; in wmv2_idct_col()
/third_party/node/deps/openssl/openssl/crypto/sm3/
H A Dsm3_local.h51 #define EXPAND(W0,W7,W13,W3,W10) \
52 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
/third_party/openssl/crypto/sm3/
H A Dsm3_local.h51 #define EXPAND(W0,W7,W13,W3,W10) \
52 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
/third_party/mesa3d/src/intel/isl/
H A Disl.c1290 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_slice0_extent_sa_gfx4_2d() local
1294 uint32_t W = isl_minify(W0, l); in isl_calc_phys_slice0_extent_sa_gfx4_2d()
1398 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx4_3d() local
1404 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); in isl_calc_phys_total_extent_el_gfx4_3d()
1453 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx6_stencil_hiz() local
1466 const uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx6_stencil_hiz()
1513 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx9_1d() local
1516 uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx9_1d()
2524 const uint32_t W0 = surf->phys_level0_sa.width; in get_image_offset_sa_gfx4_2d() local
2535 uint32_t W = isl_minify(W0, in get_image_offset_sa_gfx4_2d()
2571 const uint32_t W0 = surf->phys_level0_sa.width; get_image_offset_sa_gfx4_3d() local
2630 const uint32_t W0 = surf->phys_level0_sa.w; get_image_offset_sa_gfx6_stencil_hiz() local
2679 const uint32_t W0 = surf->phys_level0_sa.width; get_image_offset_sa_gfx9_1d() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp262 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
265 if (AArch64::W0 <= Reg && Reg <= AArch64::W30) in mapRegToGPRIndex()
266 return Reg - AArch64::W0; in mapRegToGPRIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp112 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h31 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
71 case AArch64::W0: return AArch64::X0; in getXRegFromWReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp498 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) in getSingleInstruction()
499 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; in getSingleInstruction()
606 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, in DecodeHvxWRRegisterClass()
/third_party/ffmpeg/libavcodec/ppc/
H A Dfdctdsp.c48 #define W0 -(2 * C2) macro
62 { W0, W1, W2, W3 },
103 b6 = vec_madd(cnst, b6, b5); /* b6 = b5 + b6 * W0; */ \
160 b6 = vec_madd(cnst, b6, b5); /* b6 = b5 + b6 * W0; */ \
/third_party/skia/src/core/
H A DSkVM.h393 enum W { W0, W1 }; // Are the lanes 64-bit (W1) or default (W0)? Intel Vol 2A 2.3.5.5 enumerator
398 void op(int p, int m, int o, Ymm d, Ymm x, Operand y, W w=W0) { op(p,m,o, d,x,y,w,L256); } in op()
399 void op(int p, int m, int o, Ymm d, Operand y, W w=W0) { op(p,m,o, d,0,y,w,L256); } in op()
400 void op(int p, int m, int o, Xmm d, Xmm x, Operand y, W w=W0) { op(p,m,o, d,x,y,w,L128); } in op()
401 void op(int p, int m, int o, Xmm d, Operand y, W w=W0) { op(p,m,o, d,0,y,w,L128); } in op()

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