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Searched refs:VectorFormat (Results 1 - 22 of 22) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.cc12 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
33 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
54 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
77 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
96 VectorFormat VectorFormatDoubleLanes(VectorFormat vfor
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H A Dregister-arm64.h274 enum VectorFormat { enum
296 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
297 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
298 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
299 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
300 VectorFormat ScalarFormatFromLaneSiz
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H A Dinstructions-arm64.cc383 VectorFormat NEONFormatDecoder::GetVectorFormat(int format_index) { in GetVectorFormat()
387 VectorFormat NEONFormatDecoder::GetVectorFormat( in GetVectorFormat()
389 static const VectorFormat vform[] = { in GetVectorFormat()
H A Dinstructions-arm64.h628 VectorFormat GetVectorFormat(int format_index = 0);
629 VectorFormat GetVectorFormat(const NEONFormatMap* format_map);
H A Dassembler-arm64.h2333 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format));
2340 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format));
H A Dassembler-arm64.cc1904 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
1934 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in smov()
2092 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in umov()
2132 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
2134 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
H A Dmacro-assembler-arm64.h2160 VRegister AcquireV(VectorFormat format) { in AcquireV()
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.h621 void SetActive(VectorFormat vform, int lane_index, bool value) { in SetActive()
630 bool IsActive(VectorFormat vform, int lane_index) const { in IsActive()
721 int64_t Int(VectorFormat vform, int index) const { in Int()
744 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
767 int UintArray(VectorFormat vform, uint64_t* dst) const { in UintArray()
774 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
778 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
785 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
806 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
813 void SetUint(VectorFormat vfor
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H A Dlogic-aarch64.cc185 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
194 void Simulator::ld1(VectorFormat vform, in ld1()
202 void Simulator::ld1r(VectorFormat vform, in ld1r()
203 VectorFormat unpack_vform, in ld1r()
219 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
224 void Simulator::ld2(VectorFormat vform, in ld2()
241 void Simulator::ld2(VectorFormat vform, in ld2()
254 void Simulator::ld2r(VectorFormat vform, in ld2r()
268 void Simulator::ld3(VectorFormat vform, in ld3()
290 void Simulator::ld3(VectorFormat vfor
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H A Dinstructions-aarch64.h183 enum VectorFormat { enum
321 VectorFormat GetSVEVectorFormat(int field_lsb = 22) const { in GetSVEVectorFormat()
771 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
772 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
773 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
774 VectorFormat VectorFormatHalfLanes(VectorFormat vfor
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H A Dinstructions-aarch64.cc62 VectorFormat movprfx_vform = in CanTakeSVEMovprfx()
1006 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
1033 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
1060 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
1084 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
1110 VectorFormat VectorFormatDoubleLane
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H A Dsimulator-aarch64.cc841 void Simulator::ExtractFromSimVRegister(VectorFormat vform, in Simulator()
1203 VectorFormat vform) { in Simulator()
1247 VectorFormat vform) { in Simulator()
2141 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2162 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2233 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2252 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2276 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2306 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator()
2315 VectorFormat vform_hal in Simulator()
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H A Dregisters-aarch64.h595 VRegister(int code, VectorFormat format)
641 ZRegister(int code, VectorFormat format)
726 PRegisterWithLaneSize(int code, VectorFormat format)
H A Ddisasm-aarch64.cc2202 VectorFormat vform_dst = nfd.GetVectorFormat(0); in Disassembler()
2263 VectorFormat vform_dst = nfd.GetVectorFormat(0); in Disassembler()
2357 VectorFormat vform_dst = nfd.GetVectorFormat(0); in Disassembler()
2476 VectorFormat vform_src = nfd.GetVectorFormat(1); in Disassembler()
2589 VectorFormat vform = nfd.GetVectorFormat(); in Disassembler()
3294 VectorFormat vform = nfd.GetVectorFormat(0); in Disassembler()
3352 VectorFormat vform_dst = nfd.GetVectorFormat(0); in Disassembler()
3482 VectorFormat vform_dst = nfd.GetVectorFormat(0); in Disassembler()
5377 VectorFormat vform = instr->GetSVEVectorFormat(); in Disassembler()
5596 VectorFormat vfor in Disassembler()
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H A Dassembler-aarch64.cc5093 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
5096 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
5139 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
5180 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
5216 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
H A Dassembler-aarch64.h7761 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format));
7768 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format));
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h390 int64_t Int(VectorFormat vform, int index) const { in Int()
412 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
434 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
438 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
445 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
465 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
472 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint()
492 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray()
499 void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const;
501 void WriteUintToMem(VectorFormat vfor
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H A Dsimulator-logic-arm64.cc346 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
354 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1()
359 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
366 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2()
380 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2()
389 void Simulator::ld2r(VectorFormat vform, LogicVRegister dst1, in ld2r()
400 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3()
418 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3()
431 void Simulator::ld3r(VectorFormat vform, LogicVRegister dst1, in ld3r()
445 void Simulator::ld4(VectorFormat vfor
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H A Dsimulator-arm64.cc982 void LogicVRegister::ReadUintFromMem(VectorFormat vform, int index, in ReadUintFromMem()
1002 void LogicVRegister::WriteUintToMem(VectorFormat vform, int index, in WriteUintToMem()
1245 VectorFormat vform) {
1278 VectorFormat vform) {
3125 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS;
3216 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS;
3914 VectorFormat vf = nfd.GetVectorFormat();
3919 VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp);
3922 VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl);
3926 VectorFormat vf_fcvt
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/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc470 Arm64OperandConverter i, VectorFormat scalar, in EmitFpOrNeonUnop()
471 VectorFormat vector) { in EmitFpOrNeonUnop()
472 VectorFormat f = instr->InputAt(0)->IsSimd128Register() ? vector : scalar; in EmitFpOrNeonUnop()
1175 VectorFormat dst_f = VectorFormatFillQ(LaneSizeField::decode(opcode)); in AssembleArchInstruction()
1176 VectorFormat src_f = VectorFormatHalfWidthDoubleLanes(dst_f); in AssembleArchInstruction()
1182 VectorFormat dst_f = VectorFormatFillQ(LaneSizeField::decode(opcode)); in AssembleArchInstruction()
1183 VectorFormat src_f = VectorFormatHalfWidthDoubleLanes(dst_f); in AssembleArchInstruction()
1190 VectorFormat dst_f = VectorFormatFillQ(LaneSizeField::decode(opcode)); in AssembleArchInstruction()
1191 VectorFormat src_f = VectorFormatHalfWidthDoubleLanes(dst_f); in AssembleArchInstruction()
1197 VectorFormat dst_ in AssembleArchInstruction()
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/third_party/vixl/test/aarch64/
H A Dtest-simulator-aarch64.cc1449 VectorFormat vd_form, in Test1OpNEON_Helper()
1450 VectorFormat vn_form, in Test1OpNEON_Helper()
1543 VectorFormat vd_form, in Test1OpNEON()
1544 VectorFormat vn_form) { in Test1OpNEON()
1657 VectorFormat vd_form, in Test1OpAcrossNEON_Helper()
1658 VectorFormat vn_form, in Test1OpAcrossNEON_Helper()
1751 VectorFormat vd_form, in Test1OpAcrossNEON()
1752 VectorFormat vn_form) { in Test1OpAcrossNEON()
1885 VectorFormat vd_form, in Test2OpNEON_Helper()
1886 VectorFormat vn_for in Test2OpNEON_Helper()
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/third_party/node/deps/v8/src/wasm/baseline/arm64/
H A Dliftoff-assembler-arm64.h170 Register rhs, VectorFormat format) { in EmitSimdShift()
193 template <VectorFormat format, ShiftSign sign>
225 LiftoffRegister src, VectorFormat format) { in EmitAllTrue()

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