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Searched refs:VOP3 (Results 1 - 13 of 13) sorted by relevance

/third_party/mesa3d/src/amd/compiler/tests/
H A Dtest_assembler.cpp236 aco_ptr<VOP3_instruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
254 aco_ptr<VOP3_instruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIDefines.h36 // TODO: Should this be spilt into VOP3 a and b?
37 VOP3 = 1 << 10,
188 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
229 VOP3 = 1,
H A DSIInstrInfo.h422 return MI.getDesc().TSFlags & SIInstrFlags::VOP3; in isVOP3()
426 return get(Opcode).TSFlags & SIInstrFlags::VOP3; in isVOP3()
/third_party/mesa3d/src/amd/compiler/
H A Daco_ir.cpp216 if (instr->format == Format::VOP3) in can_use_SDWA()
276 (Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA); in convert_to_SDWA()
341 if (instr->format == Format::VOP3) in can_use_DPP()
362 Format format = (Format)(((uint32_t)tmp->format & ~(uint32_t)Format::VOP3) | in convert_to_DPP()
453 /* VOP3 */ in instr_is_16bit()
H A Daco_ir.h61 * - VOP2* | VOP3 represents a VOP2 instruction in VOP3 encoding
101 VOP3 = 1 << 11, member in aco::Format
285 return (Format)((uint32_t)Format::VOP3 | (uint32_t)format); in asVOP3()
1291 constexpr bool isVOP3() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP3; }
H A Daco_opcodes.py75 VOP3 = 1 << 11 variable in Format
674 # TODO: misses some GFX6_7 opcodes which were shifted to VOP3 in GFX8
990 # VOP3 instructions: 3 inputs, 1 output
992 VOP3 = { variable
1125 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod, cls) in default_class(VOP3, InstrClass.Valu32):
1126 opcode(name, gfx7, gfx9, gfx10, Format.VOP3, cls, in_mod, out_mod)
H A Daco_validate.cpp133 * they are emitted as VOP3. in validate_ir()
135 base_format = Format::VOP3; in validate_ir()
143 /* check VOP3 modifiers */ in validate_ir()
144 if (instr->isVOP3() && instr->format != Format::VOP3) { in validate_ir()
147 "Format cannot have VOP3/VOP3B applied", instr.get()); in validate_ir()
H A Daco_optimizer.cpp1857 if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */ in label_instruction()
2552 VOP3_instruction* new_instr = create_instruction<VOP3_instruction>(opcode, Format::VOP3, 3, 1); in create_vop3_for_op3()
2869 create_instruction<VOP3_instruction>(aco_opcode::v_bcnt_u32_b32, Format::VOP3, 2, 1)}; in combine_add_bcnt()
3100 /* Applying two sgprs require making it VOP3, so don't do it unless it's
3410 create_instruction<VOP3_instruction>(mad_op, Format::VOP3, 3, 1)}; in combine_add_lshl()
4099 create_instruction<VOP3_instruction>(mad_op, Format::VOP3, 3, 1)}; in combine_instruction()
4387 /* There are no v_fmaak_legacy_f16/v_fmamk_legacy_f16 and on chips where VOP3 can take in select_instruction()
H A Daco_register_allocation.cpp544 if (instr->format == Format::VOP3) { in add_subdword_operand()
688 if (instr->format == Format::VOP3) { in add_subdword_definition()
3008 /* some instructions need VOP3 encoding if operand/definition is not assigned to VCC */ in register_allocation()
3069 /* change the instruction to VOP3 to enable an arbitrary register pair as dst */ in register_allocation()
H A Daco_lower_to_hw_instr.cpp73 /* Because some 16-bit instructions are already VOP3 on GFX10, we use the in get_reduce_opcode()
181 /* 64-bit reductions are VOP3. */ in is_vop3_reduce_opcode()
185 return instr_info.format[(int)opcode] == Format::VOP3; in is_vop3_reduce_opcode()
388 bool bound_ctrl, Operand* identity = NULL) /* for VOP3 with sparse writes */ in emit_dpp_op()
1089 /* We need the v_perm_b32 (VOP3) to be able to take literals, and that's a GFX10+ feature. */ in copy_constant()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1601 // for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity, in isLiteralImm()
2502 // of integer literals used with VOP1/2/C and VOP3,
2505 // v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
2662 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) || in checkTargetMatchPredicate()
2663 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) || in checkTargetMatchPredicate()
2668 if ((TSFlags & SIInstrFlags::VOP3) && in checkTargetMatchPredicate()
2695 static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3}; in getMatchedVariants()
2711 AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3, in getMatchedVariants()
2821 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOP in validateLdsDirect()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp355 !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) { in getInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp306 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) in printVOPDst()

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