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Searched refs:VOP2 (Results 1 - 9 of 9) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
H A Daco_validate.cpp123 else if ((uint32_t)base_format & (uint32_t)Format::VOP2) in validate_ir()
124 base_format = Format::VOP2; in validate_ir()
145 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
152 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
H A Daco_opcodes.py73 VOP2 = 1 << 9 variable in Format
673 # VOP2 instructions: 2 inputs, 1 output (+ optional vcc)
675 VOP2 = { variable
752 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, modifiers) in VOP2:
753 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, InstrClass.Valu32, modifiers, modifiers)
758 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, InstrClass.Valu32, True, False)
991 # VOP3b instructions: have a unique scalar output, e.g. VOP2 with vcc out
1097 (0x12f, 0x12f, 0x296, 0x296, 0x12f, "v_cvt_pkrtz_f16_f32_e64", True, False), # GFX6_7_10 is VOP2 with opcode 0x02f
H A Daco_ir.h61 * - VOP2* | VOP3 represents a VOP2 instruction in VOP3 encoding
62 * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive.
63 * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing.
99 VOP2 = 1 << 9, member in aco::Format
291 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
1269 constexpr bool isVOP2() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP2; }
1438 * This format can be used for VOP1, VOP2 o
[all...]
H A Daco_optimizer.cpp2824 new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2)); in combine_add_sub_b2i()
2828 create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOP2), 3, 2)); in combine_add_sub_b2i()
3331 create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)); in combine_and_subbrev()
3335 asVOP3(Format::VOP2), 3, 1)); in combine_and_subbrev()
3623 return instr->format == Format::VOP2; in can_use_mad_mix()
3883 create_instruction<VOP3_instruction>(mul_instr->opcode, asVOP3(Format::VOP2), 2, 1)); in combine_instruction()
4131 create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)}; in combine_instruction()
4548 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */ in select_instruction()
4742 new_mad.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 1)); in apply_literals()
H A Daco_assembler.cpp273 case Format::VOP2: { in emit_instruction()
H A Daco_register_allocation.cpp2580 instr->format = Format::VOP2; in optimize_encoding_vop2()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIDefines.h33 VOP2 = 1 << 8,
H A DSIInstrInfo.h414 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
418 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2820 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
6855 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
6859 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);
6863 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);
6895 if (BasicInstType == SIInstrFlags::VOP2 &&
6932 case SIInstrFlags::VOP2:
6951 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");

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