Searched refs:VOP1 (Results 1 - 12 of 12) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_validate.cpp | 121 if ((uint32_t)base_format & (uint32_t)Format::VOP1) in validate_ir()
122 base_format = Format::VOP1; in validate_ir()
145 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
152 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
|
| H A D | aco_ir.h | 65 * (*) The same is applicable for VOP1 and VOPC instructions.
98 VOP1 = 1 << 8, member in aco::Format
291 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
1258 constexpr bool isVOP1() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP1; }
1438 * This format can be used for VOP1, VOP2 or VOPC instructions.
1509 * This format can be used for VOP1, VOP2 or VOPC instructions.
|
| H A D | aco_opcodes.py | 72 VOP1 = 1 << 8 variable in Format
761 # VOP1 instructions: instructions with 1 input and 1 output
762 VOP1 = { variable
858 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod, cls) in default_class(VOP1, InstrClass.Valu32):
859 opcode(name, gfx7, gfx9, gfx10, Format.VOP1, cls, in_mod, out_mod)
|
| H A D | aco_assembler.cpp | 282 case Format::VOP1: { in emit_instruction()
|
| H A D | aco_insert_NOPs.cpp | 713 create_instruction<VOP1_instruction>(aco_opcode::v_mov_b32, Format::VOP1, 1, 1)};
|
| H A D | aco_lower_to_hw_instr.cpp | 516 aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)}; in emit_reduction()
539 aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)}; in emit_reduction()
|
| H A D | aco_spill.cpp | 289 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */ in should_rematerialize()
290 if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && in should_rematerialize()
|
| H A D | aco_register_allocation.cpp | 3057 Format::VOP1, 1, 1)); in register_allocation()
|
| H A D | aco_instruction_selection.cpp | 9342 create_instruction<VOP3_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIDefines.h | 32 VOP1 = 1 << 7,
|
| H A D | SIInstrInfo.h | 406 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
410 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1601 // for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity, in isLiteralImm()
2502 // of integer literals used with VOP1/2/C and VOP3,
2504 // v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
2820 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
6851 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
6922 case SIInstrFlags::VOP1:
6951 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
|
Completed in 60 milliseconds