| /third_party/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-operand-rn-a32.cc | 127 M(Uxtb) \
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| H A D | test-simulator-cond-rd-operand-rn-t32.cc | 127 M(Uxtb) \
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| H A D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 119 M(Uxtb) \
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| H A D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 119 M(Uxtb) \
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| H A D | test-disasm-a32.cc | 2355 TEST_SHIFT_T32(Uxtb, "uxtb", 0x0000000a) in TEST()
2388 MUST_FAIL_TEST_BOTH(Uxtb(r0, 0x1), "Ill-formed 'uxtb' instruction.\n"); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 1018 void TurboAssembler::Uxtb(const Register& rd, const Register& rn) { in Uxtb() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1173 inline void Uxtb(const Register& rd, const Register& rn);
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2788 void Uxtb(const Register& rd, const Register& rn) { in Uxtb() function in vixl::aarch64::MacroAssembler
6458 void Uxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Uxtb() function in vixl::aarch64::MacroAssembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-sve-aarch64.cc | 6261 __ Uxtb(z0.VnH(), pg, z31.VnH());
6263 __ Uxtb(z1.VnS(), pg, z1.VnS()); // destructive
6265 __ Uxtb(z2.VnD(), pg, z31.VnD());
6279 // Uxtb (H)
6285 // Uxtb (S) destructive
6291 // Uxtb (D)
7110 __ Uxtb(z19.VnH(), p2.Merging(), z2.VnH());
7118 __ Uxtb(z21.VnD(), p4.Merging(), z4.VnD());
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| H A D | test-assembler-aarch64.cc | 6903 __ Uxtb(x20, x1);
13771 __ Uxtb(w0, w0);
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 6362 void Uxtb(Condition cond, Register rd, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
6375 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); } in MacroAssembler() function in vixl::aarch32::MacroAssembler
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