| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 3434 add(vform, result, zdn, zm).UnsignedSaturate(vform); in Simulator()
3437 sub(vform, result, zdn, zm).UnsignedSaturate(vform); in Simulator()
3440 sub(vform, result, zm, zdn).UnsignedSaturate(vform); in Simulator()
7544 add(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
7550 sub(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
7562 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
7574 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in Simulator()
9060 add(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
9066 sub(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
9072 ushl(vf, rd, rn, rm).UnsignedSaturate(v in Simulator()
[all...] |
| H A D | logic-aarch64.cc | 1700 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1711 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
2284 return extractnarrow(vform, dst, false, src, true).UnsignedSaturate(vform);
2291 return extractnarrow(vform, dst, false, src, false).UnsignedSaturate(vform);
3356 return shrn(vform, dst, src, shift).UnsignedSaturate(vform);
3364 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform);
3372 return rshrn(vform, dst, src, shift).UnsignedSaturate(vform);
3380 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform);
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| H A D | simulator-aarch64.h | 923 LogicVRegister& UnsignedSaturate(VectorFormat vform) { in UnsignedSaturate() function in vixl::aarch64::LogicVRegister
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 4374 add(vf, rd, rn, rm).UnsignedSaturate(vf);
4380 sub(vf, rd, rn, rm).UnsignedSaturate(vf);
4392 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
4404 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
5577 add(vf, rd, rn, rm).UnsignedSaturate(vf);
5583 sub(vf, rd, rn, rm).UnsignedSaturate(vf);
5589 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
5601 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
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| H A D | simulator-logic-arm64.cc | 1422 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in uqshl()
1430 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in sqshlu()
1821 return ExtractNarrow(vform, dst, false, src, true).UnsignedSaturate(vform); in sqxtun()
1826 return ExtractNarrow(vform, dst, false, src, false).UnsignedSaturate(vform); in uqxtn()
2231 return shrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn()
2236 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
2241 return rshrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn()
2246 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
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| H A D | simulator-arm64.h | 574 LogicVRegister& UnsignedSaturate(VectorFormat vform) { in UnsignedSaturate() function in v8::internal::LogicVRegister
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