| /third_party/vixl/src/aarch64/ |
| H A D | operands-aarch64.cc | 174 // Extend modes SXTX and UXTX require a 64-bit register. in Operand()
175 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
195 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0))); in IsPlainRegister()
221 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
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| H A D | macro-assembler-aarch64.cc | 976 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in Emit()
2032 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in Emit()
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| H A D | disasm-aarch64.cc | 872 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in Disassembler()
875 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in Disassembler()
7203 (instr->GetExtendMode() == UXTX))) { in Disassembler()
7241 // Extend mode UXTX is an alias for shift mode LSL here. in Disassembler()
7242 if (!((ext == UXTX) && (shift == 0))) { in Disassembler()
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| H A D | constants-aarch64.h | 362 UXTX = 3, enumerator
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| H A D | assembler-aarch64.cc | 6239 case UXTX:
6322 // LSL is encoded in the option field as UXTX.
6324 ext = UXTX;
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| H A D | simulator-aarch64.cc | 1097 case UXTX: in Simulator()
4269 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in Simulator()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 43 UXTX, enumerator
63 case AArch64_AM::UXTX: return "uxtx"; in getShiftExtendName()
130 case 3: return AArch64_AM::UXTX; in getExtendType()
157 case AArch64_AM::UXTX: return 3; break; in getExtendEncoding()
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| H A D | AArch64InstPrinter.cpp | 998 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at in printArithExtend()
1000 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1004 ExtType == AArch64_AM::UXTX) || in printArithExtend()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64-inl.h | 266 // Extend modes SXTX and UXTX require a 64-bit register. in Operand()
267 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
306 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
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| H A D | macro-assembler-arm64.cc | 250 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
848 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
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| H A D | constants-arm64.h | 374 UXTX = 3, enumerator
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| H A D | assembler-arm64.cc | 3909 case UXTX: in EmitExtendShift()
3975 // LSL is encoded in the option field as UXTX. in LoadStore()
3977 ext = UXTX; in LoadStore()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 460 UXTX, enumerator
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| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 149 const char* form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in VisitAddSubExtended()
152 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in VisitAddSubExtended()
4222 (instr->ExtendMode() == UXTX))) { in SubstituteExtendField()
4253 // Extend mode UXTX is an alias for shift mode LSL here. in SubstituteLSRegOffsetField()
4254 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-api-aarch64.cc | 988 VIXL_CHECK(Operand(x5, UXTX).IsPlainRegister()); in TEST()
1000 VIXL_CHECK(!Operand(x5, UXTX, 1).IsPlainRegister()); in TEST()
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| H A D | test-assembler-aarch64.cc | 500 __ Orr(x9, x0, Operand(x1, UXTX, 3)); in TEST()
594 __ Orn(x9, x0, Operand(x1, UXTX, 3)); in TEST()
661 __ And(x9, x0, Operand(x1, UXTX, 3)); in TEST()
807 __ Bic(x9, x0, Operand(x1, UXTX, 3)); in TEST()
939 __ Eor(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1006 __ Eon(x9, x0, Operand(x1, UXTX, 3)); in TEST()
5702 __ Adc(x13, x1, Operand(x2, UXTX, 4));
5714 __ Adc(x23, x1, Operand(x2, UXTX, 4));
7809 __ adds(xzr, x0, Operand(x1, UXTX));
7810 __ adds(xzr, x1, Operand(xzr, UXTX));
[all...] |
| H A D | test-disasm-aarch64.cc | 336 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4"); in TEST()
348 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3"); in TEST()
362 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4"); in TEST()
374 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3"); in TEST()
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| H A D | test-cpu-features-aarch64.cc | 178 TEST_NONE(add_1, add(x0, x1, Operand(x2, UXTX, 4)))
483 TEST_NONE(subs_1, subs(x0, x1, Operand(x2, UXTX, 3)))
490 TEST_NONE(sub_1, sub(x0, x1, Operand(x2, UXTX, 3)))
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1254 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1273 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1745 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
2753 .Case("uxtx", AArch64_AM::UXTX) in tryParseOptionalShiftExtend()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 1120 .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 4)) in emitPrologue()
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| H A D | AArch64InstrInfo.cpp | 793 case AArch64_AM::UXTX: in isFalkorShiftExtFast()
827 case AArch64_AM::UXTX: in isFalkorShiftExtFast()
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| H A D | AArch64ISelDAGToDAG.cpp | 721 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 866 Cmp(result.gp().X(), Operand(expected.gp().X(), UXTX)); in AtomicCompareExchange()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1154 case UXTX:
1983 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 2037 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTX, Register); in AssembleArchInstruction()
|