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Searched refs:TRI (Results 1 - 25 of 439) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp100 const TargetRegisterInfo &TRI) { in markRegsUnavailable()
103 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in markRegsUnavailable()
112 void invalidateRegister(unsigned Reg, const TargetRegisterInfo &TRI) { in invalidateRegister() argument
117 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in invalidateRegister()
129 for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI) in invalidateRegister()
134 void clobberRegister(unsigned Reg, const TargetRegisterInfo &TRI) { in clobberRegister() argument
135 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in clobberRegister()
140 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister()
144 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI); in clobberRegister()
152 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) { in trackCopy() argument
99 markRegsUnavailable(ArrayRef<unsigned> Regs, const TargetRegisterInfo &TRI) markRegsUnavailable() argument
176 findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI, bool MustBeAvailable = false) findCopyForUnit() argument
186 findCopyDefViaUnit(unsigned RegUnit, const TargetRegisterInfo &TRI) findCopyDefViaUnit() argument
197 findAvailBackwardCopy(MachineInstr &I, unsigned Reg, const TargetRegisterInfo &TRI) findAvailBackwardCopy() argument
218 findAvailCopy(MachineInstr &DestCopy, unsigned Reg, const TargetRegisterInfo &TRI) findAvailCopy() argument
249 const TargetRegisterInfo *TRI; global() member in __anon24047::MachineCopyPropagation
333 isNopCopy(const MachineInstr &PreviousCopy, unsigned Src, unsigned Def, const TargetRegisterInfo *TRI) isNopCopy() argument
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H A DRegisterClassInfo.cpp48 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
49 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
55 assert(TRI && "no register info set"); in runOnMachineFunction()
62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); in runOnMachineFunction()
64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
80 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
148 TRI in compute()
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H A DAggressiveAntiDepBreaker.cpp130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
134 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
144 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
154 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
164 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
182 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
210 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
219 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
256 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
314 for (MCRegAliasIterator AI(Reg, TRI, tru
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H A DLiveRegMatrix.cpp56 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
60 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
80 static bool foreachUnit(const TargetRegisterInfo *TRI, in foreachUnit() argument
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
106 << printReg(PhysReg, TRI) << ':'); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); in assign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " fro in unassign()
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H A DTargetRegisterInfo.cpp89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() argument
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
103 } else if (!TRI) in printReg()
105 else if (Reg < TRI->getNumRegs()) { in printReg()
107 printLowerCase(TRI->getName(Reg), OS); in printReg()
112 if (TRI) in printReg()
113 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
120 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in printRegUnit() argument
121 return Printable([Unit, TRI](raw_ostream &OS) { in printRegUnit()
122 // Generic printout when TRI i in printRegUnit()
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H A DStackMaps.cpp92 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { in getDwarfRegNum() argument
93 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum()
94 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
95 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
105 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); in parseOperand() local
119 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
128 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
153 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
157 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand()
158 unsigned LLVMRegNum = *TRI in parseOperand()
175 const TargetRegisterInfo *TRI = print() local
258 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); parseRegisterLiveOutMask() local
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H A DRegisterScavenging.cpp60 TRI = MF.getSubtarget().getRegisterInfo(); in init()
62 LiveUnits.init(*TRI); in init()
64 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && in init()
69 NumRegUnits = TRI->getNumRegUnits(); in init()
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in removeRegUnits()
123 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { in determineKillsAndDefs()
124 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { in determineKillsAndDefs()
224 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) in forward()
230 for (MCSuperRegIterator SR(Reg, TRI); S in forward()
389 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); findSurvivorBackwards() local
626 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); scavengeVReg() local
681 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); scavengeFrameVirtualRegsInBlock() local
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H A DDetectDeadLanes.cpp110 const TargetRegisterInfo *TRI; member in __anon24000::DetectDeadLanes
164 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in isCrossCopy() local
178 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
184 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
187 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
189 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
190 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
203 UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes); in addUsedLanesOnOperand()
243 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
248 TRI in transferUsedLanes()
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H A DRegUsageInfoCollector.cpp103 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() local
128 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); in runOnMachineFunction()
148 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF)) in runOnMachineFunction()
149 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction()
162 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
182 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction()
184 dbgs() << printReg(PReg, TRI) << " "; in runOnMachineFunction()
198 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in computeCalleeSavedRegs() local
207 const MCPhysReg *CSRegs = TRI in computeCalleeSavedRegs()
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H A DCriticalAntiDepBreaker.cpp48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
49 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
50 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
56 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
74 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
92 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
119 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
195 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, M in PrescanInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
82 print(dbgs(), /* IsForDebug */ true, TRI); in dump() local
87 const TargetRegisterInfo *TRI) const { in print()
97 if (!TRI || ContainedRegClasses.empty()) in print()
99 assert(ContainedRegClasses.size() == TRI in print()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h49 const TargetRegisterInfo *TRI = nullptr; member in llvm::LivePhysRegs
58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { in LivePhysRegs() argument
59 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs()
66 void init(const TargetRegisterInfo &TRI) { in init() argument
67 this->TRI = &TRI; in init()
69 LiveRegs.setUniverse(TRI.getNumRegs()); in init()
80 assert(TRI in addReg()
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H A DLiveRegUnits.h31 const TargetRegisterInfo *TRI = nullptr; member in llvm::LiveRegUnits
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument
40 init(TRI); in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
63 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init() argument
75 this->TRI = &TRI; in init()
77 Units.resize(TRI.getNumRegUnits()); in init()
88 for (MCRegUnitIterator Unit(Reg, TRI); Uni in addReg()
47 accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI) accumulateUsedDefed() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp118 const SIRegisterInfo *TRI; member in __anon24476::SIFixSGPRCopies
154 const SIRegisterInfo *TRI) { in hasVectorOperands()
161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
169 const SIRegisterInfo &TRI, in getCopyRegClasses()
176 : TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()
179 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg()); in getCopyRegClasses()
183 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
190 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy()
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
192 TRI in isVGPRToSGPRCopy()
153 hasVectorOperands(const MachineInstr &MI, const SIRegisterInfo *TRI) hasVectorOperands() argument
168 getCopyRegClasses(const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) getCopyRegClasses() argument
188 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) isVGPRToSGPRCopy() argument
195 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) isSGPRToVGPRCopy() argument
202 tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII) tryChangeVGPRtoSGPRinCopy() argument
240 foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI) foldVGPRCopyIntoRegSequence() argument
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H A DSIMachineFunctionInfo.cpp188 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
190 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
196 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr() argument
197 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
203 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr() argument
204 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
210 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr() argument
212 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
218 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID() argument
219 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI in addDispatchID()
187 addPrivateSegmentBuffer( const SIRegisterInfo &TRI) addPrivateSegmentBuffer() argument
225 addFlatScratchInit(const SIRegisterInfo &TRI) addFlatScratchInit() argument
232 addImplicitBufferPtr(const SIRegisterInfo &TRI) addImplicitBufferPtr() argument
269 const SIRegisterInfo *TRI = ST.getRegisterInfo(); allocateSGPRSpillToVGPR() local
347 const SIRegisterInfo *TRI = ST.getRegisterInfo(); allocateVGPRSpillToAGPR() local
417 regToString(unsigned Reg, const TargetRegisterInfo &TRI) regToString() argument
428 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI) convertArgumentInfo() argument
478 SIMachineFunctionInfo( const llvm::SIMachineFunctionInfo& MFI, const TargetRegisterInfo &TRI) SIMachineFunctionInfo() argument
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H A DSILowerSGPRSpills.cpp49 const SIRegisterInfo *TRI = nullptr; member in __anon24490::SILowerSGPRSpills
94 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRSaves() local
97 if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { in insertCSRSaves()
103 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves()
106 TRI); in insertCSRSaves()
126 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRRestores() local
133 if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) { in insertCSRRestores()
136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores()
138 TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI); in insertCSRRestores()
209 const TargetRegisterClass *RC = TRI in spillCalleeSavedRegs()
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H A DAMDGPUInstructionSelector.cpp53 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
76 return Reg == TRI.getVCC(); in isVCC()
83 return RC->hasSuperClassEq(TRI.getBoolRC()) && in isVCC()
104 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
116 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
124 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY()
140 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
152 TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
165 TRI in selectCOPY()
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H A DR600ExpandSpecialInstrs.cpp86 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
136 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
139 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
142 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
166 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
167 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
168 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI in runOnMachineFunction()
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H A DGCNRegBankReassign.cpp142 const SIRegisterInfo *TRI; member in __anon24457::GCNRegBankReassign
235 OS << llvm::printReg(Reg, TRI); in printReg()
239 OS << "<unassigned> " << llvm::printReg(Reg, TRI); in printReg()
241 OS << llvm::printReg(Reg, TRI) << '(' in printReg()
242 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')'; in printReg()
244 OS << ':' << TRI->getSubRegIndexName(SubReg); in printReg()
281 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
282 unsigned Size = TRI->getRegSizeInBits(*RC);
284 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
286 if (TRI
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H A DGCNHazardRecognizer.cpp46 TRI(TII.getRegisterInfo()), in GCNHazardRecognizer()
47 ClauseUses(TRI.getNumRegUnits()), in GCNHazardRecognizer()
48 ClauseDefs(TRI.getNumRegUnits()) { in GCNHazardRecognizer()
446 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getWaitStatesSinceDef() local
448 auto IsHazardFn = [IsHazardDef, TRI, Reg] (MachineInstr *MI) { in getWaitStatesSinceDef()
449 return IsHazardDef(MI) && MI->modifiesRegister(Reg, TRI); in getWaitStatesSinceDef()
468 static void addRegUnits(const SIRegisterInfo &TRI, in addRegUnits() argument
470 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) in addRegUnits()
474 static void addRegsToSet(const SIRegisterInfo &TRI, in addRegsToSet() argument
479 addRegUnits(TRI, Se in addRegsToSet()
604 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkDPPHazards() local
722 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazardsHelper() local
786 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkRWLaneHazards() local
825 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkAnyInstHazards() local
914 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVMEMtoScalarWriteHazards() local
965 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixSMEMtoVectorWriteHazards() local
1037 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVcmpxExecWARHazard() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI in MipsRegInfoRecord()
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H A DMipsFrameLowering.cpp95 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFP() local
99 TRI->needsStackRealignment(MF); in hasFP()
104 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP() local
106 return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); in hasBP()
116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in estimateStackSize() local
126 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { in estimateStackSize()
127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createLRSpillSlot() local
43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
46 TRI.getSpillAlignment(RC), true); in createLRSpillSlot()
57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createFPSpillSlot() local
59 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createFPSpillSlot()
60 TRI.getSpillAlignment(RC), true); in createFPSpillSlot()
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createEHSpillSlot() local
72 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
73 unsigned Align = TRI in createEHSpillSlot()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DRDFRegisters.cpp29 : TRI(tri) { in PhysicalRegisterInfo()
30 RegInfos.resize(TRI.getNumRegs()); in PhysicalRegisterInfo()
32 BitVector BadRC(TRI.getNumRegs()); in PhysicalRegisterInfo()
33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
46 UnitInfos.resize(TRI.getNumRegUnits()); in PhysicalRegisterInfo()
48 for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) { in PhysicalRegisterInfo()
51 MCRegUnitRootIterator R(U, &TRI); in PhysicalRegisterInfo()
59 for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) { in PhysicalRegisterInfo()
75 for (const uint32_t *RM : TRI.getRegMasks()) in PhysicalRegisterInfo()
85 BitVector PU(TRI in PhysicalRegisterInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp74 const ARMBaseRegisterInfo &TRI; member in __anon24531::ARMInstructionSelector
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
189 const TargetRegisterInfo &TRI, in guessRegClass()
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy()
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
236 const TargetRegisterInfo &TRI, in selectMergeValues()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI) in selectMergeValues()
187 guessRegClass(unsigned Reg, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) guessRegClass() argument
213 selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) selectCopy() argument
233 selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) selectMergeValues() argument
264 selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) selectUnmergeValues() argument
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