| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 261 __ Strh(PickW(), MemOperand(scratch, 42, PostIndex)); in GenerateMemOperandSequence()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3634 COMPARE_T32(Strh(eq, r6, MemOperand(r7, 62)), in TEST()
3638 COMPARE_T32(Strh(eq, r6, MemOperand(r7, 64)), in TEST()
3642 COMPARE_T32(Strh(eq, r6, MemOperand(r7, 1)), in TEST()
3647 COMPARE_T32(Strh(eq, r5, MemOperand(r6, r7)), in TEST()
3651 COMPARE_T32(Strh(eq, r6, MemOperand(r9)), in TEST()
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| H A D | test-simulator-cond-rd-memop-immediate-512-a32.cc | 119 M(Strh)
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| H A D | test-simulator-cond-rd-memop-rs-a32.cc | 123 M(Strh)
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerARM32.cpp | 1930 constexpr const char *Strh = "strh";
1931 emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh);
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 41 V(Strh, Register&, rt, STRH_w) \
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 596 Strh(src.gp().W(), dst_op); in Store()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1871 __ Strh(i.InputOrZeroRegister64(0), i.MemoryOperand(1)); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 5471 void Strh(Condition cond, Register rt, const MemOperand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
5495 void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); } in MacroAssembler() function in vixl::aarch32::MacroAssembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 3276 __ Strh(w4, MemOperand(x18, 33));
3374 __ Strh(w4, MemOperand(x26, 41, PreIndex));
3432 __ Strh(w4, MemOperand(x26, -41, PostIndex));
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 53 V(Strh, Register&, rt, STRH_w) \
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