| /third_party/vixl/src/aarch64/ |
| H A D | operands-aarch64.cc | 174 // Extend modes SXTX and UXTX require a 64-bit register. in Operand()
175 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
195 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0))); in IsPlainRegister()
261 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
263 // SXTX extend mode requires a 64-bit offset register. in MemOperand()
264 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX)); in MemOperand()
322 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
323 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX))); in MemOperand()
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| H A D | macro-assembler-aarch64.cc | 976 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in Emit()
2032 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in Emit()
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| H A D | disasm-aarch64.cc | 872 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in Disassembler()
875 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in Disassembler()
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| H A D | constants-aarch64.h | 366 SXTX = 7 enumerator
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| H A D | simulator-aarch64.cc | 1098 case SXTX: in Simulator()
4269 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in Simulator()
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| H A D | assembler-aarch64.cc | 6240 case SXTX: {
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 48 SXTX, enumerator
67 case AArch64_AM::SXTX: return "sxtx"; in getShiftExtendName()
134 case 7: return AArch64_AM::SXTX; in getExtendType()
161 case AArch64_AM::SXTX: return 7; break; in getExtendEncoding()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64-inl.h | 266 // Extend modes SXTX and UXTX require a 64-bit register. in Operand()
267 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
395 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
397 // SXTX extend mode requires a 64-bit offset register. in MemOperand()
398 DCHECK(regoffset.Is64Bits() || (extend != SXTX)); in MemOperand()
447 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
448 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX))); in MemOperand()
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| H A D | macro-assembler-arm64.cc | 250 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
848 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
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| H A D | constants-arm64.h | 378 SXTX = 7 enumerator
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| H A D | assembler-arm64.cc | 3910 case SXTX: { in EmitExtendShift()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-api-aarch64.cc | 989 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); in TEST()
1001 VIXL_CHECK(!Operand(x6, SXTX, 2).IsPlainRegister()); in TEST()
1023 VIXL_CHECK(!MemOperand(x3, xzr, SXTX).IsPlainRegister()); in TEST()
1024 VIXL_CHECK(!MemOperand(x4, xzr, SXTX, 2).IsPlainRegister()); in TEST()
1042 VIXL_CHECK(MemOperand(x3, xzr, SXTX).IsEquivalentToPlainRegister()); in TEST()
1043 VIXL_CHECK(MemOperand(x4, xzr, SXTX, 2).IsEquivalentToPlainRegister()); in TEST()
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| H A D | test-disasm-aarch64.cc | 341 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx"); in TEST()
367 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx"); in TEST()
1109 COMPARE(ldr(w18, MemOperand(x19, x20, SXTX)), "ldr w18, [x19, x20, sxtx]"); in TEST()
1110 COMPARE(ldr(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
1119 COMPARE(ldr(x18, MemOperand(x19, x20, SXTX)), "ldr x18, [x19, x20, sxtx]"); in TEST()
1120 COMPARE(ldr(x21, MemOperand(x22, x23, SXTX, 3)), in TEST()
1130 COMPARE(str(w18, MemOperand(x19, x20, SXTX)), "str w18, [x19, x20, sxtx]"); in TEST()
1131 COMPARE(str(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
1140 COMPARE(str(x18, MemOperand(x19, x20, SXTX)), "str x18, [x19, x20, sxtx]"); in TEST()
1141 COMPARE(str(x21, MemOperand(x22, x23, SXTX, in TEST()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 171 TEST_NONE(adds_1, adds(x0, x1, Operand(x2, SXTX, 4)))
234 TEST_NONE(cmn_1, cmn(x0, Operand(x1, SXTX, 1)))
241 TEST_NONE(cmp_1, cmp(x0, Operand(x1, SXTX, 0)))
300 TEST_NONE(ldrb_5, ldrb(w0, MemOperand(x1, x2, SXTX, 0)))
305 TEST_NONE(ldrh_4, ldrh(w0, MemOperand(x1, x2, SXTX, 1)))
314 TEST_NONE(ldrsb_8, ldrsb(w0, MemOperand(x1, x2, SXTX, 0)))
317 TEST_NONE(ldrsb_11, ldrsb(x0, MemOperand(x1, x2, SXTX, 0)))
327 TEST_NONE(ldrsh_9, ldrsh(x0, MemOperand(x1, x2, SXTX, 1)))
405 TEST_NONE(prfm_3, prfm(PSTL3STRM, MemOperand(x0, x1, SXTX, 0)))
456 TEST_NONE(strb_5, strb(w0, MemOperand(x1, x2, SXTX,
[all...] |
| H A D | test-assembler-aarch64.cc | 504 __ Orr(x13, x0, Operand(x1, SXTX, 3)); in TEST()
598 __ Orn(x13, x0, Operand(x1, SXTX, 3)); in TEST()
665 __ And(x13, x0, Operand(x1, SXTX, 3)); in TEST()
811 __ Bic(x13, x0, Operand(x1, SXTX, 3)); in TEST()
943 __ Eor(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1010 __ Eon(x13, x0, Operand(x1, SXTX, 3)); in TEST()
4613 __ Prfm(op, MemOperand(x0, input, SXTX));
4614 __ Prfm(op, MemOperand(x0, input, SXTX, 3));
5749 __ Adcs(x10, x0, Operand(x1, SXTX, 1));
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 465 SXTX enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1254 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1273 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1282 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1753 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1765 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2757 .Case("sxtx", AArch64_AM::SXTX) in tryParseOptionalShiftExtend()
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| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 149 const char* form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in VisitAddSubExtended()
152 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in VisitAddSubExtended()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1155 case SXTX:
1983 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 721 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
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| H A D | AArch64FastISel.cpp | 1147 Addr.getExtendType() == AArch64_AM::SXTX; in addLoadStoreOperands()
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