Searched refs:SWC1 (Results 1 - 15 of 15) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 520 SWC1 = 1, enumerator
931 return Latency::SWC1; in Uswc1Latency()
955 int latency = AdjustBaseAndOffsetLatency() + Latency::SWC1; in Sdc1Latency()
957 return latency + Latency::SWC1; in Sdc1Latency()
1641 return MoveLatency(false) + Latency::SWC1; // Estimated max. in GetInstructionLatency()
1657 return Latency::SWC1 + SubuLatency(false); in GetInstructionLatency()
1688 return Latency::SWC1; in GetInstructionLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 238 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_32.c | 162 ins = SWC1 | S(SLJIT_SP) | FT(float_arg_count) | IMM(*offsets_ptr); in call_with_args()
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| H A D | sljitNativeMIPS_common.c | 280 #define SWC1 (HI(57)) macro
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 546 SWC1 = 1, enumerator
885 int Swc1Latency() { return AdjustBaseAndOffsetLatency() + Latency::SWC1; } in Swc1Latency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
267 Opc = Mips::SWC1; in storeRegToStack()
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| H A D | MipsInstructionSelector.cpp | 222 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
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| H A D | MipsFastISel.cpp | 832 Opc = Mips::SWC1; in emitStore()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 485 SWC1 = ((7U << 3) + 1) << kOpcodeShift,
1323 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
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| H A D | assembler-mips64.cc | 2671 GenInstrImmediate(SWC1, src.rm(), fs, src.offset_); in swc1()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 490 SWC1 = ((7U << 3) + 1) << kOpcodeShift,
1271 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
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| H A D | assembler-mips.cc | 2408 GenInstrImmediate(SWC1, tmp.rm(), fd, tmp.offset()); in swc1()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 7133 case SWC1: {
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 6760 case SWC1:
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 5220 unsigned Opcode = Mips::SWC1; in expandStoreDM1Macro()
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