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Searched refs:SVE_ALL (Results 1 - 8 of 8) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.h3984 void cntb(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
3987 void cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
3990 void cnth(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
3998 void cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
4019 void decb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4022 void decd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4025 void decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4028 void dech(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4031 void dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4040 void decw(const Register& xdn, int pattern = SVE_ALL, in
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H A Dmacro-assembler-aarch64.h4119 void Cntb(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) { in Cntb() argument
4124 void Cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) { in Cntd() argument
4129 void Cnth(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) { in Cnth() argument
4144 void Cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) { in Cntw() argument
4175 void Decb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) { in Decb() argument
4180 void Decd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) { in Decd() argument
4185 void Decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) { in Decd() argument
4190 void Dech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) { in Dech() argument
4195 void Dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) { in Dech() argument
4213 void Decw(const Register& rdn, int pattern = SVE_ALL, in in Decp() argument
4218 Decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Decw() argument
4900 Incb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Incb() argument
4905 Incd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Incd() argument
4910 Incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Incd() argument
4915 Inch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Inch() argument
4920 Inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Inch() argument
4938 Incw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Incw() argument
4943 Incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Incw() argument
5711 Ptrue(const PRegisterWithLaneSize& pd, SVEPredicateConstraint pattern = SVE_ALL) Ptrue() argument
5717 Ptrues(const PRegisterWithLaneSize& pd, SVEPredicateConstraint pattern = SVE_ALL) Ptrues() argument
5867 Sqdecb(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqdecb() argument
5875 Sqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecb() argument
5880 Sqdecd(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqdecd() argument
5888 Sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecd() argument
5893 Sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecd() argument
5898 Sqdech(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqdech() argument
5906 Sqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqdech() argument
5911 Sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdech() argument
5938 Sqdecw(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqdecw() argument
5946 Sqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecw() argument
5951 Sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecw() argument
5956 Sqincb(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqincb() argument
5964 Sqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqincb() argument
5969 Sqincd(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqincd() argument
5977 Sqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqincd() argument
5982 Sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqincd() argument
5987 Sqinch(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqinch() argument
5995 Sqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqinch() argument
6000 Sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqinch() argument
6027 Sqincw(const Register& xd, const Register& wn, int pattern = SVE_ALL, int multiplier = 1) Sqincw() argument
6035 Sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Sqincw() argument
6040 Sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqincw() argument
6308 Uqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecb() argument
6313 Uqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecd() argument
6318 Uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecd() argument
6323 Uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqdech() argument
6328 Uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdech() argument
6362 Uqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecw() argument
6367 Uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecw() argument
6372 Uqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqincb() argument
6377 Uqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqincd() argument
6382 Uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqincd() argument
6387 Uqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqinch() argument
6392 Uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqinch() argument
6426 Uqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) Uqincw() argument
6431 Uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqincw() argument
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H A Ddisasm-aarch64.cc4553 if (instr->ExtractBits(9, 5) == SVE_ALL) { in Disassembler()
4555 // and the pattern is SVE_ALL. in Disassembler()
5494 if (instr->ExtractBits(9, 5) == SVE_ALL) form = "'Pd.'t"; in Disassembler()
6965 case SVE_ALL: in Disassembler()
H A Dconstants-aarch64.h564 SVE_ALL = 0x1f enumerator
H A Dlogic-aarch64.cc7618 case SVE_ALL:
7648 ptrue(vform, ptemp, SVE_ALL);
/third_party/vixl/test/aarch64/
H A Dtest-disasm-sve-aarch64.cc470 COMPARE_MACRO(Cntb(x7, SVE_ALL), "cntb x7"); in TEST()
479 COMPARE_MACRO(Cntb(x7, SVE_ALL, 2), "cntb x7, all, mul #2"); in TEST()
501 COMPARE_MACRO(Decb(x4, SVE_ALL), "decb x4"); in TEST()
510 COMPARE_MACRO(Decb(x4, SVE_ALL, 2), "decb x4, all, mul #2"); in TEST()
526 COMPARE_MACRO(Incb(x17, SVE_ALL), "incb x17"); in TEST()
535 COMPARE_MACRO(Incb(x17, SVE_ALL, 2), "incb x17, all, mul #2"); in TEST()
557 COMPARE_MACRO(Sqdecb(x12, w12, SVE_ALL), "sqdecb x12, w12"); in TEST()
568 COMPARE_MACRO(Sqdecb(x12, w12, SVE_ALL, 2), "sqdecb x12, w12, all, mul #2"); in TEST()
582 COMPARE_MACRO(Sqincd(x20, w20, SVE_ALL, 2), "sqincd x20, w20, all, mul #2"); in TEST()
592 COMPARE_MACRO(Sqdecb(x5, SVE_ALL), "sqdec in TEST()
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H A Dtest-api-movprfx-aarch64.cc1119 __ decw(z6.VnS(), SVE_ALL); in TEST()
1140 __ incw(z30.VnS(), SVE_ALL); in TEST()
1188 __ sqdecw(z22.VnS(), SVE_ALL); in TEST()
1200 __ sqincw(z29.VnS(), SVE_ALL); in TEST()
1239 __ uqdecw(z19.VnS(), SVE_ALL); in TEST()
1251 __ uqincw(z12.VnS(), SVE_ALL); in TEST()
1416 __ decw(z4.VnS(), SVE_ALL); in TEST()
1440 __ incw(z26.VnS(), SVE_ALL); in TEST()
1582 __ sqdecw(z8.VnS(), SVE_ALL); in TEST()
1594 __ sqincw(z10.VnS(), SVE_ALL); in TEST()
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H A Dtest-assembler-sve-aarch64.cc3417 __ Ptrue(p[15], SVE_ALL, s);
3743 (masm->*cnt)(Register(21, sizeof(T) * kBitsPerByte), SVE_ALL, multiplier);
4214 (masm.*cnt)(x21, w21, SVE_ALL, multiplier);
4371 (masm.*fn)(z30.WithLaneSize(lane_size_in_bits), SVE_ALL, multiplier);
4388 (masm.*cnt)(x14, SVE_ALL, multiplier);
7076 // Setting SVE_ALL on B lanes checks that the Simulator ignores irrelevant
7078 __ Ptrue(p6.VnB(), SVE_ALL);
7160 // st1b { z1.b }, SVE_ALL
7201 // st1w { z6.s }, SVE_ALL
7342 // st2b { z14.b, z15.b }, SVE_ALL
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