Home
last modified time | relevance | path

Searched refs:STI (Results 1 - 25 of 409) sorted by relevance

12345678910>>...17

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
34 const MCSubtargetInfo &STI, raw_ostream &O);
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
44 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
48 const MCSubtargetInfo &STI, raw_ostream &O);
50 const MCSubtargetInfo &STI, raw_ostream &O);
53 const MCSubtargetInfo &STI, raw_ostream &O);
55 const MCSubtargetInfo &STI, raw_ostream &O);
57 const MCSubtargetInfo &STI, raw_ostrea
[all...]
H A DARMTargetStreamer.cpp119 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { in getArchForCPU() argument
120 if (STI.getCPU() == "xscale") in getArchForCPU()
123 if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
124 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
131 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
135 } else if (STI in getArchForCPU()
153 isV8M(const MCSubtargetInfo &STI) isV8M() argument
162 emitTargetAttributes(const MCSubtargetInfo &STI) emitTargetAttributes() argument
[all...]
H A DARMMCCodeEmitter.cpp63 bool isThumb(const MCSubtargetInfo &STI) const { in isThumb()
64 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb()
67 bool isThumb2(const MCSubtargetInfo &STI) const { in isThumb2()
68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; in isThumb2()
71 bool isTargetMachO(const MCSubtargetInfo &STI) const { in isTargetMachO()
72 const Triple &TT = STI.getTargetTriple(); in isTargetMachO()
82 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
95 const MCSubtargetInfo &STI) cons
626 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) getBranchTargetOpValue() argument
[all...]
H A DARMInstPrinter.cpp92 StringRef Annot, const MCSubtargetInfo &STI, in printInst()
106 printSBitModifierOperand(MI, 6, STI, O); in printInst()
107 printPredicateOperand(MI, 4, STI, O); in printInst()
128 printSBitModifierOperand(MI, 5, STI, O); in printInst()
129 printPredicateOperand(MI, 3, STI, O); in printInst()
153 printPredicateOperand(MI, 2, STI, O); in printInst()
157 printRegisterList(MI, 4, STI, O); in printInst()
167 printPredicateOperand(MI, 4, STI, O); in printInst()
182 printPredicateOperand(MI, 2, STI, O); in printInst()
186 printRegisterList(MI, 4, STI, in printInst()
91 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) printInst() argument
311 printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOperand() argument
351 printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printThumbLdrLabelOperand() argument
[all...]
H A DARMAsmBackend.h21 // The STI from the target triple the MCAsmBackend was instantiated with
22 // note that MCFragments may have a different local STI that should be
24 const MCSubtargetInfo &STI; member in llvm::ARMAsmBackend
27 ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, in ARMAsmBackend() argument
29 : MCAsmBackend(Endian), STI(STI), in ARMAsmBackend()
30 isThumbMode(STI.getTargetTriple().isThumb()) {} in ARMAsmBackend()
36 // FIXME: this should be calculated per fragment as the STI may be
38 bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; } in hasNOP()
50 const MCSubtargetInfo *STI) cons
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h27 const MCSubtargetInfo &STI, raw_ostream &O);
31 const MCSubtargetInfo &STI, raw_ostream &O) override;
37 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI, raw_ostream &O);
45 const MCSubtargetInfo &STI, raw_ostream &O);
52 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
59 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
62 const MCSubtargetInfo &STI, raw_ostrea
[all...]
H A DAMDGPUInstPrinter.cpp30 StringRef Annot, const MCSubtargetInfo &STI, in printInst()
33 printInstruction(MI, Address, STI, OS); in printInst()
38 const MCSubtargetInfo &STI, in printU4ImmOperand()
49 const MCSubtargetInfo &STI, in printU16ImmOperand()
57 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
76 const MCSubtargetInfo &STI, in printU32ImmOperand()
112 const MCSubtargetInfo &STI, in printOffset()
122 const MCSubtargetInfo &STI, in printFlatOffset()
134 if (AMDGPU::isGFX10(STI)) { in printFlatOffset()
144 const MCSubtargetInfo &STI, in printOffset0()
29 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) printInst() argument
37 printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printU4ImmOperand() argument
48 printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printU16ImmOperand() argument
75 printU32ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printU32ImmOperand() argument
111 printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOffset() argument
121 printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printFlatOffset() argument
143 printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOffset0() argument
152 printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOffset1() argument
161 printSMRDOffset8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSMRDOffset8() argument
167 printSMRDOffset20(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSMRDOffset20() argument
173 printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSMRDLiteralOffset() argument
179 printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printGDS() argument
184 printDLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDLC() argument
190 printGLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printGLC() argument
195 printSLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSLC() argument
200 printSWZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSWZ() argument
204 printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printTFE() argument
209 printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDMask() argument
217 printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDim() argument
229 printUNorm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printUNorm() argument
234 printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDA() argument
239 printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printR128A16() argument
247 printLWE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printLWE() argument
252 printD16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printD16() argument
257 printExpCompr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpCompr() argument
264 printExpVM(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpVM() argument
271 printFORMAT(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printFORMAT() argument
303 printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printVOPDst() argument
339 printVINTRPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printVINTRPDst() argument
349 printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) printImmediate16() argument
381 printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) printImmediateV216() argument
388 printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) printImmediate32() argument
422 printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) printImmediate64() argument
461 printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printBLGP() argument
471 printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printCBSZ() argument
481 printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printABID() argument
491 printDefaultVccOperand(unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDefaultVccOperand() argument
502 printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOperand() argument
582 printImmediate32(FloatToBits(Op.getFPImm()), STI, O); printOperand() local
584 printImmediate64(DoubleToBits(Op.getFPImm()), STI, O); printOperand() local
621 printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOperandAndFPInputMods() argument
656 printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOperandAndIntInputMods() argument
682 printDPP8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDPP8() argument
696 printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printDPPCtrl() argument
781 printRowMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printRowMask() argument
788 printBankMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printBankMask() argument
795 printBoundCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printBoundCtrl() argument
804 printFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printFI() argument
831 printSDWADstSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSDWADstSel() argument
838 printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSDWASrc0Sel() argument
845 printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSDWASrc1Sel() argument
852 printSDWADstUnused(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSDWADstUnused() argument
868 printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpSrcN() argument
891 printExpSrc0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpSrc0() argument
897 printExpSrc1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpSrc1() argument
903 printExpSrc2(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpSrc2() argument
909 printExpSrc3(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpSrc3() argument
915 printExpTgt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printExpTgt() argument
998 printOpSel(const MCInst *MI, unsigned, const MCSubtargetInfo &STI, raw_ostream &O) printOpSel() argument
1016 printOpSelHi(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOpSelHi() argument
1022 printNegLo(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printNegLo() argument
1028 printNegHi(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printNegHi() argument
1034 printInterpSlot(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printInterpSlot() argument
1053 printInterpAttr(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printInterpAttr() argument
1060 printInterpAttrChan(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printInterpAttrChan() argument
1067 printVGPRIndexMode(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printVGPRIndexMode() argument
1090 printMemOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printMemOperand() argument
1118 printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printHigh() argument
1125 printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printClampSI() argument
1132 printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printOModSI() argument
1144 printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSendMsg() argument
1207 printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printSwizzle() argument
1280 printWaitFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printWaitFlag() argument
1310 printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printHwreg() argument
1333 printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printEndpgm() argument
1346 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) printInst() argument
[all...]
H A DSIMCCodeEmitter.cpp49 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const override;
66 const MCSubtargetInfo &STI) const override;
72 const MCSubtargetInfo &STI) const override;
76 const MCSubtargetInfo &STI) const override;
80 const MCSubtargetInfo &STI) const override;
84 const MCSubtargetInfo &STI) const override;
108 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) { in getLit16Encoding() argument
138 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit16Encoding()
144 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) { in getLit32Encoding() argument
180 getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) getLit64Encoding() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
34 const MCSubtargetInfo &STI, raw_ostream &O);
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
50 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
53 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
64 const MCSubtargetInfo &STI, raw_ostream &O) { in printPostIncOperand()
69 const MCSubtargetInfo &STI, raw_ostrea
63 printPostIncOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) printPostIncOperand() argument
89 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printMemExtend() argument
108 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printUImm12Offset() argument
114 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) printAMIndexedWB() argument
[all...]
H A DAArch64MCCodeEmitter.cpp58 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
90 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
103 const MCSubtargetInfo &STI) const;
109 const MCSubtargetInfo &STI) const;
115 const MCSubtargetInfo &STI) cons
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h35 bool isMicroMips(const MCSubtargetInfo &STI) const;
36 bool isMips32r6(const MCSubtargetInfo &STI) const;
47 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
52 const MCSubtargetInfo &STI) const override;
58 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) cons
[all...]
H A DMipsMCCodeEmitter.cpp120 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { in isMicroMips()
121 return STI.getFeatureBits()[Mips::FeatureMicroMips]; in isMicroMips()
124 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { in isMips32r6()
125 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in isMips32r6()
133 const MCSubtargetInfo &STI, in EmitInstruction()
139 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { in EmitInstruction()
140 EmitInstruction(Val >> 16, 2, STI, OS); in EmitInstruction()
141 EmitInstruction(Val, 2, STI, OS); in EmitInstruction()
155 const MCSubtargetInfo &STI) const in encodeInstruction()
183 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
132 EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const EmitInstruction() argument
[all...]
H A DMipsTargetStreamer.cpp37 static bool isMicroMips(const MCSubtargetInfo *STI) { in isMicroMips() argument
38 return STI->getFeatureBits()[Mips::FeatureMicroMips]; in isMicroMips()
132 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore()
167 const MCSubtargetInfo *STI) { in emitR()
172 getStreamer().EmitInstruction(TmpInst, *STI); in emitR()
176 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRX()
182 getStreamer().EmitInstruction(TmpInst, *STI); in emitRX()
186 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRI()
187 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
191 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRR()
130 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) emitDirectiveCpRestore() argument
166 emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI) emitR() argument
175 emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRX() argument
185 emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRI() argument
190 emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRR() argument
195 emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitII() argument
205 emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRX() argument
217 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRR() argument
223 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRRX() argument
236 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRI() argument
242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRIII() argument
257 emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI) emitAddu() argument
264 emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI) emitDSLL() argument
275 emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI) emitEmptyDelaySlot() argument
283 emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) emitNop() argument
291 emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI) emitGPRestore() argument
297 emitStoreWithImmOffset( unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) emitStoreWithImmOffset() argument
334 emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) emitLoadWithImmOffset() argument
665 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) emitDirectiveCpRestore() argument
767 MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) MipsTargetELFStreamer() argument
1173 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) emitDirectiveCpRestore() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp226 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) { in streamIsaVersion() argument
227 auto TargetTriple = STI->getTargetTriple(); in streamIsaVersion()
228 auto Version = getIsaVersion(STI->getCPU()); in streamIsaVersion()
239 if (hasXNACK(*STI)) in streamIsaVersion()
241 if (hasSRAMECC(*STI)) in streamIsaVersion()
247 bool hasCodeObjectV3(const MCSubtargetInfo *STI) { in hasCodeObjectV3() argument
248 return STI->getTargetTriple().getOS() == Triple::AMDHSA && in hasCodeObjectV3()
249 STI->getFeatureBits().test(FeatureCodeObjectV3); in hasCodeObjectV3()
252 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() argument
253 if (STI in getWavefrontSize()
261 getLocalMemorySize(const MCSubtargetInfo *STI) getLocalMemorySize() argument
270 getEUsPerCU(const MCSubtargetInfo *STI) getEUsPerCU() argument
274 getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) getMaxWorkGroupsPerCU() argument
286 getMaxWavesPerCU(const MCSubtargetInfo *STI) getMaxWavesPerCU() argument
290 getMaxWavesPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) getMaxWavesPerCU() argument
295 getMinWavesPerEU(const MCSubtargetInfo *STI) getMinWavesPerEU() argument
299 getMaxWavesPerEU(const MCSubtargetInfo *STI) getMaxWavesPerEU() argument
306 getMaxWavesPerEU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) getMaxWavesPerEU() argument
312 getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) getMinFlatWorkGroupSize() argument
316 getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) getMaxFlatWorkGroupSize() argument
321 getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) getWavesPerWorkGroup() argument
327 getSGPRAllocGranule(const MCSubtargetInfo *STI) getSGPRAllocGranule() argument
336 getSGPREncodingGranule(const MCSubtargetInfo *STI) getSGPREncodingGranule() argument
340 getTotalNumSGPRs(const MCSubtargetInfo *STI) getTotalNumSGPRs() argument
347 getAddressableNumSGPRs(const MCSubtargetInfo *STI) getAddressableNumSGPRs() argument
359 getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) getMinNumSGPRs() argument
376 getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable) getMaxNumSGPRs() argument
393 getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed) getNumExtraSGPRs() argument
417 getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed) getNumExtraSGPRs() argument
423 getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) getNumSGPRBlocks() argument
429 getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional<bool> EnableWavefrontSize32) getVGPRAllocGranule() argument
437 getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional<bool> EnableWavefrontSize32) getVGPREncodingGranule() argument
442 getTotalNumVGPRs(const MCSubtargetInfo *STI) getTotalNumVGPRs() argument
448 getAddressableNumVGPRs(const MCSubtargetInfo *STI) getAddressableNumVGPRs() argument
452 getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) getMinNumVGPRs() argument
463 getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) getMaxNumVGPRs() argument
472 getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional<bool> EnableWavefrontSize32) getNumVGPRBlocks() argument
482 initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI) initDefaultAMDKernelCodeT() argument
518 getDefaultAmdhsaKernelDescriptor( const MCSubtargetInfo *STI) getDefaultAmdhsaKernelDescriptor() argument
720 getLastSymbolicHwreg(const MCSubtargetInfo &STI) getLastSymbolicHwreg() argument
729 isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) isValidHwreg() argument
752 getHwreg(unsigned Id, const MCSubtargetInfo &STI) getHwreg() argument
782 isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) isValidMsgId() argument
921 hasXNACK(const MCSubtargetInfo &STI) hasXNACK() argument
925 hasSRAMECC(const MCSubtargetInfo &STI) hasSRAMECC() argument
929 hasMIMG_R128(const MCSubtargetInfo &STI) hasMIMG_R128() argument
933 hasPackedD16(const MCSubtargetInfo &STI) hasPackedD16() argument
937 isSI(const MCSubtargetInfo &STI) isSI() argument
941 isCI(const MCSubtargetInfo &STI) isCI() argument
945 isVI(const MCSubtargetInfo &STI) isVI() argument
949 isGFX9(const MCSubtargetInfo &STI) isGFX9() argument
953 isGFX10(const MCSubtargetInfo &STI) isGFX10() argument
957 isGCN3Encoding(const MCSubtargetInfo &STI) isGCN3Encoding() argument
1023 getMCReg(unsigned Reg, const MCSubtargetInfo &STI) getMCReg() argument
[all...]
H A DAMDGPUBaseInfo.h68 /// Streams isa version string for given subtarget \p STI into \p Stream.
69 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
71 /// \returns True if given subtarget \p STI supports code object version 3,
73 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
75 /// \returns Wavefront size for given subtarget \p STI.
76 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
78 /// \returns Local memory size in bytes for given subtarget \p STI.
79 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
82 /// STI.
83 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp49 const MCSubtargetInfo &STI) const override;
55 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
81 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
87 const MCSubtargetInfo &STI) cons
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.h40 const MCSubtargetInfo &STI) const;
43 const MCSubtargetInfo &STI) const;
46 const MCSubtargetInfo &STI) const;
49 const MCSubtargetInfo &STI) const;
52 const MCSubtargetInfo &STI) const;
55 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
67 const MCSubtargetInfo &STI) cons
[all...]
H A DPPCMCCodeEmitter.cpp45 const MCSubtargetInfo &STI) const { in getDirectBrEncoding()
47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
57 const MCSubtargetInfo &STI) const { in getCondBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
70 const MCSubtargetInfo &STI) const { in getAbsDirectBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
83 const MCSubtargetInfo &STI) const { in getAbsCondBrEncoding()
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
95 const MCSubtargetInfo &STI) const { in getImm16Encoding()
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/InstPrinter/
H A DVEInstPrinter.cpp43 StringRef Annot, const MCSubtargetInfo &STI, in printInst()
45 if (!printAliasInstr(MI, STI, OS)) in printInst()
46 printInstruction(MI, Address, STI, OS); in printInst()
51 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand()
75 const MCSubtargetInfo &STI, in printMemASXOperand()
79 printOperand(MI, opNum, STI, O); in printMemASXOperand()
81 printOperand(MI, opNum + 1, STI, O); in printMemASXOperand()
87 printOperand(MI, opNum + 1, STI, O); in printMemASXOperand()
90 printOperand(MI, opNum, STI, O); in printMemASXOperand()
95 const MCSubtargetInfo &STI, in printMemASOperand()
42 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) printInst() argument
50 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) printOperand() argument
74 printMemASXOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) printMemASXOperand() argument
94 printMemASOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) printMemASOperand() argument
114 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) printCCOperand() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { in isV9()
38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; in isV9()
47 StringRef Annot, const MCSubtargetInfo &STI, in printInst()
49 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) in printInst()
50 printInstruction(MI, Address, STI, O); in printInst()
55 const MCSubtargetInfo &STI, in printSparcAliasInstr()
76 O << "\tjmp "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr()
79 O << "\tcall "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr()
85 if (isV9(STI) in printSparcAliasInstr()
46 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) printInst() argument
54 printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) printSparcAliasInstr() argument
108 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) printOperand() argument
140 printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) printMemOperand() argument
163 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) printCCOperand() argument
192 printGetPCX(const MCInst *MI, unsigned opNum, const MCSubtargetInfo &STI, raw_ostream &O) printGetPCX() argument
199 printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) printMembarTag() argument
[all...]
H A DSparcMCCodeEmitter.cpp58 const MCSubtargetInfo &STI) const override;
64 const MCSubtargetInfo &STI) const;
70 const MCSubtargetInfo &STI) const;
74 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const { in encodeInstruction()
98 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
100 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
[all...]
H A DSparcInstPrinter.h28 const MCSubtargetInfo &STI, raw_ostream &O) override;
29 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
31 bool isV9(const MCSubtargetInfo &STI) const;
35 const MCSubtargetInfo &STI, raw_ostream &O);
36 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
40 const MCSubtargetInfo &STI, raw_ostream &O);
43 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
45 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
47 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
49 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h47 const MCSubtargetInfo &STI) const;
53 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const;
63 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const;
85 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) cons
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp68 const MCSubtargetInfo &STI);
106 const MCSubtargetInfo &STI) in EmitCall()
111 OutStreamer.EmitInstruction(CallInst, STI); in EmitCall()
116 const MCSubtargetInfo &STI) in EmitSETHI()
122 OutStreamer.EmitInstruction(SETHIInst, STI); in EmitSETHI()
127 const MCSubtargetInfo &STI) in EmitBinary()
134 OutStreamer.EmitInstruction(Inst, STI); in EmitBinary()
139 const MCSubtargetInfo &STI) { in EmitOR()
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); in EmitOR()
145 const MCSubtargetInfo &STI) { in EmitADD()
104 EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI) EmitCall() argument
114 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitSETHI() argument
125 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) EmitBinary() argument
137 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitOR() argument
143 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) EmitADD() argument
149 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitSHL() argument
156 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) EmitHiLo() argument
169 LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, const MCSubtargetInfo &STI) LowerGETPCXAndEmitMCInsts() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCSchedule.cpp40 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency() argument
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
56 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency() argument
62 return MCSchedModel::computeInstrLatency(STI, SCDesc); in computeInstrLatency()
67 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency() argument
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in computeInstrLatency()
82 return MCSchedModel::computeInstrLatency(STI, *SCDesc); in computeInstrLatency()
88 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput() argument
91 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
92 const MCWriteProcResEntry *I = STI in getReciprocalThroughput()
110 getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInst &Inst) const getReciprocalThroughput() argument
[all...]

Completed in 18 milliseconds

12345678910>>...17