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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp53 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { in MipsLegalizerInfo() argument
66 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
69 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
83 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
84 if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()}, in MipsLegalizerInfo()
85 {s32, p0, 16, ST.hasMips32r6()}, in MipsLegalizerInfo()
86 {s32, p0, 32, ST.hasMips32r6()}, in MipsLegalizerInfo()
87 {p0, p0, 32, ST.hasMips32r6()}, in MipsLegalizerInfo()
88 {s64, p0, 64, ST.hasMips32r6()}})) in MipsLegalizerInfo()
90 if (ST in MipsLegalizerInfo()
317 SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode, MachineIRBuilder &MIRBuilder, const MipsSubtarget &ST) SelectMSA3OpIntrinsic() argument
332 MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, MachineIRBuilder &MIRBuilder, const MipsSubtarget &ST) MSA3OpIntrinsicToGeneric() argument
344 MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, MachineIRBuilder &MIRBuilder, const MipsSubtarget &ST) MSA2OpIntrinsicToGeneric() argument
358 const MipsSubtarget &ST = legalizeIntrinsic() local
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/third_party/node/deps/openssl/openssl/crypto/bn/asm/
H A Dppc-mont.pl58 $ST= "stw"; # store
67 $PUSH= $ST;
79 $ST= "std"; # store
88 $PUSH= $ST;
215 $ST $lo1,0($tp) ; tp[j-1]
228 $ST $lo1,0($tp) ; tp[j-1]
233 $ST $hi1,$BNSZ($tp)
281 $ST $lo1,0($tp) ; tp[j-1]
295 $ST $lo1,0($tp) ; tp[j-1]
301 $ST
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H A Dmips.pl64 $ST="sd";
79 $ST="sw";
188 $ST $t1,0($a0)
201 $ST $t3,$BNSZ($a0)
215 $ST $ta1,-2*$BNSZ($a0)
227 $ST $ta3,-$BNSZ($a0)
248 $ST $t1,0($a0)
263 $ST $t1,$BNSZ($a0)
277 $ST $t1,2*$BNSZ($a0)
340 $ST
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H A Dppc.pl118 $ST= "stw"; # store
142 $ST= "std"; # store
302 $ST r9,`0*$BNSZ`(r3) # r[0]=c1;
317 $ST r10,`1*$BNSZ`(r3) #r[1]=c2;
336 $ST r11,`2*$BNSZ`(r3) #r[2]=c3
360 $ST r9,`3*$BNSZ`(r3) #r[3]=c1
378 $ST r10,`4*$BNSZ`(r3) #r[4]=c2
390 $ST r11,`5*$BNSZ`(r3) #r[5] = c3
397 $ST r9,`6*$BNSZ`(r3) #r[6]=c1
398 $ST r1
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/third_party/openssl/crypto/bn/asm/
H A Dppc-mont.pl58 $ST= "stw"; # store
67 $PUSH= $ST;
79 $ST= "std"; # store
88 $PUSH= $ST;
215 $ST $lo1,0($tp) ; tp[j-1]
228 $ST $lo1,0($tp) ; tp[j-1]
233 $ST $hi1,$BNSZ($tp)
281 $ST $lo1,0($tp) ; tp[j-1]
295 $ST $lo1,0($tp) ; tp[j-1]
301 $ST
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H A Dmips.pl64 $ST="sd";
79 $ST="sw";
188 $ST $t1,0($a0)
201 $ST $t3,$BNSZ($a0)
215 $ST $ta1,-2*$BNSZ($a0)
227 $ST $ta3,-$BNSZ($a0)
248 $ST $t1,0($a0)
263 $ST $t1,$BNSZ($a0)
277 $ST $t1,2*$BNSZ($a0)
340 $ST
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H A Dppc.pl118 $ST= "stw"; # store
142 $ST= "std"; # store
302 $ST r9,`0*$BNSZ`(r3) # r[0]=c1;
317 $ST r10,`1*$BNSZ`(r3) #r[1]=c2;
336 $ST r11,`2*$BNSZ`(r3) #r[2]=c3
360 $ST r9,`3*$BNSZ`(r3) #r[3]=c1
378 $ST r10,`4*$BNSZ`(r3) #r[4]=c2
390 $ST r11,`5*$BNSZ`(r3) #r[5] = c3
397 $ST r9,`6*$BNSZ`(r3) #r[6]=c1
398 $ST r1
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.h47 const ARMSubtarget *ST; member in llvm::ARMTTIImpl
83 const ARMSubtarget *getST() const { return ST; } in getST()
88 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), in ARMTTIImpl()
89 TLI(ST->getTargetLowering()) {} in ARMTTIImpl()
99 return ST->isMClass() && ST->isThumb2() && L->getNumBlocks() == 1; in shouldFavorBackedgeIndex()
106 return !ST->isTargetDarwin() && !ST->hasMVEFloatOps(); in isFPVectorizationPotentiallyUnsafe()
128 if (ST->hasNEON()) in getNumberOfRegisters()
130 if (ST in getNumberOfRegisters()
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H A DARMTargetTransformInfo.cpp79 if (!ST->isThumb()) { in getIntImmCost()
84 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
86 if (ST->isThumb2()) { in getIntImmCost()
91 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
138 if (ST->isThumb2() && NegImm < 1<<12) in getIntImmCostInst()
141 if (ST->isThumb() && NegImm < 1<<8) in getIntImmCostInst()
166 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
207 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
293 if (SrcTy.isVector() && ST->hasNEON()) { in getCastInstrCost()
323 if (SrcTy.isFloatingPoint() && ST in getCastInstrCost()
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H A DARMLegalizerInfo.cpp62 static bool AEABI(const ARMSubtarget &ST) { in AEABI() argument
63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); in AEABI()
66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { in ARMLegalizerInfo() argument
77 if (ST.isThumb1Only()) { in ARMLegalizerInfo()
80 verify(*ST.getInstrInfo()); in ARMLegalizerInfo()
93 if (ST.hasNEON()) in ARMLegalizerInfo()
107 bool HasHWDivide = (!ST.isThumb() && ST in ARMLegalizerInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
H A DARCTargetTransformInfo.h33 const ARCSubtarget *ST; member in llvm::ARCTTIImpl
36 const ARCSubtarget *getST() const { return ST; } in getST()
41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()), in ARCTTIImpl()
42 TLI(ST->getTargetLowering()) {} in ARCTTIImpl()
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} in ARCTTIImpl()
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), in ARCTTIImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp27 static ArrayRef<MCPhysReg> getAllSGPR128(const GCNSubtarget &ST, in getAllSGPR128() argument
30 ST.getMaxNumSGPRs(MF) / 4); in getAllSGPR128()
33 static ArrayRef<MCPhysReg> getAllSGPRs(const GCNSubtarget &ST, in getAllSGPRs() argument
36 ST.getMaxNumSGPRs(MF)); in getAllSGPRs()
187 void SIFrameLowering::emitFlatScratchInit(const GCNSubtarget &ST, in emitFlatScratchInit() argument
190 const SIInstrInfo *TII = ST.getInstrInfo(); in emitFlatScratchInit()
222 if (ST.flatScratchIsPointer()) { in emitFlatScratchInit()
223 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) { in emitFlatScratchInit()
251 assert(ST.getGeneration() < AMDGPUSubtarget::GFX10); in emitFlatScratchInit()
270 const GCNSubtarget &ST, in getReservedPrivateSegmentBufferReg()
269 getReservedPrivateSegmentBufferReg( const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI, SIMachineFunctionInfo *MFI, MachineFunction &MF) const getReservedPrivateSegmentBufferReg() argument
319 getReservedPrivateSegmentWaveByteOffsetReg( const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI, SIMachineFunctionInfo *MFI, MachineFunction &MF) const getReservedPrivateSegmentWaveByteOffsetReg() argument
404 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); emitEntryFunctionPrologue() local
533 emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF, MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI, MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg, unsigned ScratchRsrcReg) const emitEntryFunctionScratchSetup() argument
686 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); emitPrologue() local
828 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); emitEpilogue() local
950 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); processFunctionBeforeFrameFinalized() local
988 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); determineCalleeSaves() local
1062 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); determineCalleeSavesSGPR() local
1099 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); eliminateCallFramePseudoInstr() local
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H A DGCNIterativeScheduler.cpp110 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printRegions() local
116 R->MaxPressure.print(OS, &ST); in printRegions()
134 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printSchedRP() local
136 Before.print(OS, &ST); in printSchedRP()
138 After.print(OS, &ST); in printSchedRP()
420 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleRegion() local
425 SchedMaxRP.print(dbgs(), &ST), in scheduleRegion()
427 MaxRP.print(dbgs(), &ST), in scheduleRegion()
429 RegionMaxRP.print(dbgs(), &ST), in scheduleRegion()
435 const auto &ST in sortRegionsByPressure() local
452 const auto &ST = MF.getSubtarget<GCNSubtarget>(); tryMaximizeOccupancy() local
489 const auto &ST = MF.getSubtarget<GCNSubtarget>(); scheduleLegacyMaxOccupancy() local
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H A DSIOptimizeExecMaskingPreRA.cpp87 const GCNSubtarget &ST) { in isEndCF()
88 if (ST.isWave32()) { in isEndCF()
97 static bool isFullExecCopy(const MachineInstr& MI, const GCNSubtarget& ST) { in isFullExecCopy() argument
98 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in isFullExecCopy()
110 const GCNSubtarget& ST) { in getOrNonExecReg()
111 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getOrNonExecReg()
124 const GCNSubtarget& ST) { in getOrExecSource()
125 auto SavedExec = getOrNonExecReg(MI, TII, ST); in getOrExecSource()
129 if (!SaveExecInst || !isFullExecCopy(*SaveExecInst, ST)) in getOrExecSource()
190 const GCNSubtarget &ST, in optimizeVcndVcmpPair()
86 isEndCF(const MachineInstr &MI, const SIRegisterInfo *TRI, const GCNSubtarget &ST) isEndCF() argument
108 getOrNonExecReg(const MachineInstr &MI, const SIInstrInfo &TII, const GCNSubtarget& ST) getOrNonExecReg() argument
121 getOrExecSource(const MachineInstr &MI, const SIInstrInfo &TII, const MachineRegisterInfo &MRI, const GCNSubtarget& ST) getOrExecSource() argument
189 optimizeVcndVcmpPair(MachineBasicBlock &MBB, const GCNSubtarget &ST, MachineRegisterInfo &MRI, LiveIntervals *LIS) optimizeVcndVcmpPair() argument
298 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); runOnMachineFunction() local
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H A DGCNHazardRecognizer.cpp44 ST(MF.getSubtarget<GCNSubtarget>()), in GCNHazardRecognizer()
45 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
50 TSchedModel.init(&ST); in GCNHazardRecognizer()
146 if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0) in getHazardType()
152 if (ST.hasNoDataDepHazard()) in getHazardType()
176 if (ST.hasReadM0MovRelInterpHazard() && in getHazardType()
181 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) && in getHazardType()
257 if (ST.hasNSAtoVMEMBug()) in PreEmitNoopsCommon()
262 if (ST.hasNoDataDepHazard()) in PreEmitNoopsCommon()
289 if (ST in PreEmitNoopsCommon()
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H A DAMDGPUTargetTransformInfo.h49 const GCNSubtarget *ST; member in llvm::final
52 const TargetSubtargetInfo *getST() const { return ST; } in getST()
59 ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))), in AMDGPUTTIImpl()
60 TLI(ST->getTargetLowering()) {} in AMDGPUTTIImpl()
72 const GCNSubtarget *ST; member in llvm::final
105 const GCNSubtarget *getST() const { return ST; } in getST()
125 return ST->hasHalfRate64Ops() ? in get64BitInstrCost()
132 ST(static_cast<const GCNSubtarget*>(TM->getSubtargetImpl(F))), in GCNTTIImpl()
133 TLI(ST->getTargetLowering()), in GCNTTIImpl()
136 HasFP32Denormals(ST in GCNTTIImpl()
239 const R600Subtarget *ST; global() member in llvm::final
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H A DSIMachineFunctionInfo.cpp50 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in SIMachineFunctionInfo() local
52 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F); in SIMachineFunctionInfo()
53 WavesPerEU = ST.getWavesPerEU(F); in SIMachineFunctionInfo()
55 Occupancy = ST.computeOccupancy(MF, getLDSSize()); in SIMachineFunctionInfo()
87 MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(), in SIMachineFunctionInfo()
122 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 && in SIMachineFunctionInfo()
128 bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F); in SIMachineFunctionInfo()
140 } else if (ST.isMesaGfxShader(F)) { in SIMachineFunctionInfo()
147 if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) { in SIMachineFunctionInfo()
182 const GCNSubtarget& ST in limitOccupancy() local
254 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); haveFreeLanesForSGPRSpill() local
268 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); allocateSGPRSpillToVGPR() local
328 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); allocateVGPRSpillToAGPR() local
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H A DSIOptimizeExecMasking.cpp60 static Register isCopyFromExec(const MachineInstr &MI, const GCNSubtarget &ST) { in isCopyFromExec() argument
69 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
78 static Register isCopyToExec(const MachineInstr &MI, const GCNSubtarget &ST) { in isCopyToExec() argument
85 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
240 const GCNSubtarget &ST, in findExecCopy()
248 Register CopyFromExec = isCopyFromExec(*I, ST); in findExecCopy()
272 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
273 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in runOnMachineFunction()
274 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
275 MCRegister Exec = ST in runOnMachineFunction()
238 findExecCopy( const SIInstrInfo &TII, const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::reverse_iterator I, unsigned CopyToExec) findExecCopy() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/TableGen/
H A DSetTheory.cpp40 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts,
42 ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc);
48 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts,
54 ST.evaluate(*Expr->arg_begin(), Add, Loc);
55 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc);
64 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts,
70 ST.evaluate(Expr->arg_begin()[0], S1, Loc);
71 ST.evaluate(Expr->arg_begin()[1], S2, Loc);
80 virtual void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N,
83 void apply(SetTheory &ST, DagIni
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp52 if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64) in getPopcntSupport()
53 return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ? in getPopcntSupport()
189 if (ST->isPPC64() && in getIntImmCostInst()
218 const PPCTargetMachine &TM = ST->getTargetMachine(); in mightUseCTR()
453 if (ST->useSoftFloat()) { in mightUseCTR()
482 const PPCTargetMachine &TM = ST->getTargetMachine(); in isHardwareLoopProfitable()
484 SchedModel.init(ST); in isHardwareLoopProfitable()
539 if (ST->getCPUDirective() == PPC::DIR_A2) { in getUnrollingPreferences()
565 if (ST->getCPUDirective() == PPC::DIR_A2) in enableAggressiveInterleaving()
586 if (ST in getNumberOfRegisters()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). in getPopcntSupport()
65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; in getPopcntSupport()
121 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
124 if (ST->is64Bit()) { in getNumberOfRegisters()
125 if (Vector && ST->hasAVX512()) in getNumberOfRegisters()
133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); in getRegisterBitWidth()
135 if (ST->hasAVX512() && PreferVectorWidth >= 512) in getRegisterBitWidth()
137 if (ST->hasAVX() && PreferVectorWidth >= 256) in getRegisterBitWidth()
139 if (ST in getRegisterBitWidth()
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H A DX86MacroFusion.cpp38 const X86Subtarget &ST = static_cast<const X86Subtarget &>(TSI); in shouldScheduleAdjacent() local
41 if (!(ST.hasBranchFusion() || ST.hasMacroFusion())) in shouldScheduleAdjacent()
54 if (ST.hasBranchFusion()) { in shouldScheduleAdjacent()
60 if (ST.hasMacroFusion()) { in shouldScheduleAdjacent()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
H A DVETargetTransformInfo.h30 const VESubtarget *ST; member in llvm::VETTIImpl
33 const VESubtarget *getST() const { return ST; } in getST()
38 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), in VETTIImpl()
39 TLI(ST->getTargetLowering()) {} in VETTIImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreTargetTransformInfo.h32 const XCoreSubtarget *ST; member in llvm::XCoreTTIImpl
35 const XCoreSubtarget *getST() const { return ST; } in getST()
40 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()), in XCoreTTIImpl()
41 TLI(ST->getTargetLowering()) {} in XCoreTTIImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DMCSectionXCOFF.h43 XCOFF::SymbolType ST, XCOFF::StorageClass SC, SectionKind K, in MCSectionXCOFF()
46 Type(ST), StorageClass(SC), QualName(QualName) { in MCSectionXCOFF()
47 assert((ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
42 MCSectionXCOFF(StringRef Section, XCOFF::StorageMappingClass SMC, XCOFF::SymbolType ST, XCOFF::StorageClass SC, SectionKind K, MCSymbolXCOFF *QualName, MCSymbol *Begin) MCSectionXCOFF() argument

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