Searched refs:SSE42 (Results 1 - 6 of 6) sorted by relevance
| /third_party/skia/src/core/ |
| H A D | SkCpu.h | 20 SSE42 = 1 << 5, enumerator
80 features |= SSE42; in Supports()
97 features &= (SSE1 | SSE2 | SSE3 | SSSE3 | SSE41 | SSE42 | AVX); in Supports()
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| H A D | SkCpu.cpp | 48 if (abcd[2] & (1<<20)) { features |= SkCpu::SSE42; } in read_cpu_features()
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| /third_party/ffmpeg/libavutil/x86/ |
| H A D | cpu.h | 43 #define X86_SSE42(flags) CPUEXT(flags, SSE42)
69 #define EXTERNAL_SSE42(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE42)
100 #define INLINE_SSE42(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE42)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86Subtarget.h | 64 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
79 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
589 bool hasSSE42() const { return X86SSELevel >= SSE42; } in hasSSE42()
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| /third_party/node/deps/simdutf/ |
| H A D | simdutf.h | 664 SSE42 = 0x8, enumerator
782 host_isa |= instruction_set::SSE42; in detect_supported_architectures()
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| H A D | simdutf.cpp | 2405 simdutf_really_inline implementation() : simdutf::implementation("westmere", "Intel/AMD SSE4.2", internal::instruction_set::SSE42) {} in implementation()
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