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Searched refs:SMEM (Results 1 - 14 of 14) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
H A Daco_opt_value_numbering.cpp100 case Format::SMEM: return hash_murmur_32<SMEM_instruction>(instr); in operator ()()
211 case Format::SMEM: { in operator ()()
347 case Format::SMEM: in can_eliminate()
H A Daco_insert_NOPs.cpp144 /* we break up SMEM clauses that contain stores or overwrite an
318 /* A SMEM clause is any group of consecutive SMEM instructions. The
324 * itself). In this case, we have to break the SMEM clause by inserting non
325 * SMEM instructions.
327 * SMEM clauses are only present on GFX8+, and only matter when XNACK is set.
333 /* break off from previous SMEM clause if needed */ in handle_smem_clause_hazards()
454 if (!instr->isSALU() && instr->format != Format::SMEM) in handle_instruction_gfx6()
480 if ((ctx.smem_clause || ctx.smem_write) && (NOPs || instr->format != Format::SMEM)) { in handle_instruction_gfx6()
747 * Handle any VALU instruction writing an SGPR after an SMEM read
[all...]
H A Daco_opcodes.py59 SMEM = 6 variable in Format
87 elif self == Format.SMEM:
578 # SMEM instructions: sbase input (2 sgpr), potentially 2 offset inputs, 1 sdata input/output
579 # Unlike GFX10, GFX10.3 does not have SMEM store, atomic or scratch instructions
580 SMEM = { variable
669 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SMEM:
670 opcode(name, gfx7, gfx9, gfx10, Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
H A Daco_ir.h77 SMEM = 6, member in aco::Format
1115 constexpr bool isSMEM() const noexcept { return format == Format::SMEM; }
H A Daco_assembler.cpp178 case Format::SMEM: { in emit_instruction()
H A Daco_insert_waitcnt.cpp657 case Format::SMEM: { in gen()
H A Daco_ir.cpp190 case Format::SMEM: return instr->smem().sync; in get_sync_info()
H A Daco_print_ir.cpp339 case Format::SMEM: { in print_instr_format_specific()
H A Daco_scheduler.cpp471 unsigned aliasing_storage; /* storage classes which are accessed (non-SMEM) */
472 unsigned aliasing_storage_smem; /* storage classes which are accessed (SMEM) */
669 /* break if we'd make the previous SMEM instruction stall */
685 if (candidate->format == Format::SMEM && current->operands[0].size() == 4 &&
817 /* break if we'd make the previous SMEM instruction stall */
H A Daco_validate.cpp548 case Format::SMEM: { in validate_ir()
553 "SMEM operands must be sgpr", instr.get()); in validate_ir()
558 "SMEM offset must be constant or sgpr", instr.get()); in validate_ir()
561 "SMEM result must be sgpr", instr.get()); in validate_ir()
H A Daco_register_allocation.cpp1939 case Format::SMEM: in operand_can_use_reg()
H A Daco_optimizer.cpp871 smem.opcode, Format::SMEM, smem.operands.size() + 1, smem.definitions.size()); in smem_combine()
H A Daco_instruction_selection.cpp4373 aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4982 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
6879 /* Don't expand global loads when they use MUBUF or SMEM.
6887 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6888 * it's safe to use SMEM */
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h73 int checkSoftClauseHazards(MachineInstr *SMEM);

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