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Searched refs:SI_SH_REG_OFFSET (Results 1 - 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h100 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
104 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
118 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_idx()
127 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_sh_reg_idx()
134 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in gfx10_set_sh_reg_idx3()
138 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (3 << 28)); in gfx10_set_sh_reg_idx3()
H A Dradv_device_generated_commands.c1173 (cmd_buffer->state.graphics_pipeline->vtx_base_sgpr - SI_SH_REG_OFFSET) >> 2; in radv_prepare_dgc()
1182 SI_SH_REG_OFFSET) >> in radv_prepare_dgc()
1256 SI_SH_REG_OFFSET) >> in radv_prepare_dgc()
1263 SI_SH_REG_OFFSET) >> in radv_prepare_dgc()
H A Dradv_cmd_buffer.c6700 vertex_offset_reg = (base_reg - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_indirect_draw_packet()
6702 start_instance_reg = ((base_reg + (draw_id_enable ? 8 : 4)) - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_indirect_draw_packet()
6704 draw_id_reg = ((base_reg + mesh * 12 + 4) - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_indirect_draw_packet()
6748 (R_00B900_COMPUTE_USER_DATA_0 + ring_entry_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_direct_ace_packet()
6788 (R_00B900_COMPUTE_USER_DATA_0 + ring_entry_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6792 : (R_00B900_COMPUTE_USER_DATA_0 + xyz_dim_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6796 : (R_00B900_COMPUTE_USER_DATA_0 + draw_id_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6825 uint32_t xyz_dim_reg = ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_gfx_packet()
6826 uint32_t ring_entry_reg = ((base_reg + ring_entry_loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2; in radv_cs_emit_dispatch_taskmesh_gfx_packet()
8446 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> in radv_emit_dispatch_packets()
[all...]
H A Dradv_private.h1783 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_pm4.c87 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) { in si_pm4_set_reg()
89 reg -= SI_SH_REG_OFFSET; in si_pm4_set_reg()
111 si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3); in si_pm4_set_reg_idx3()
H A Dsi_build_pm4.h115 assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
117 radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
122 assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
124 radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | (3 << 28)); \
H A Dsi_cp_reg_shadowing.c54 offset = SI_SH_REG_OFFSET; in si_build_load_reg()
H A Dsi_state_draw.cpp1585 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1586 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1603 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1604 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1605 radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h169 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
172 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
H A Dr600d_common.h31 #define SI_SH_REG_OFFSET 0x0000B000 macro
/third_party/mesa3d/src/amd/common/
H A Dsid.h32 #define SI_SH_REG_OFFSET 0x0000B000 macro
42 #define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET)
H A Dac_debug.c297 ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib); in ac_parse_packet3()

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