| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1056 SETO, // 0 1 1 1 True if ordered (no nans) enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInsertSkips.cpp | 219 case ISD::SETO: in kill()
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| H A D | R600ISelLowering.cpp | 126 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
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| H A D | SIISelLowering.cpp | 8329 if (LCC == ISD::SETO) { in performAndCombine()
8367 if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask && in performAndCombine()
8371 unsigned NewMask = LCC == ISD::SETO ? in performAndCombine()
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| H A D | AMDGPUISelLowering.cpp | 1278 case ISD::SETO: in combineFMinMaxLegacy()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 210 case FCmpInst::FCMP_ORD: return ISD::SETO; in getFCmpCondCode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 415 case ISD::SETO: return "seto"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 1676 case ISD::SETO:
1678 && "If SETO is expanded, SETOEQ must be legal!");
1700 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1719 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
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| H A D | TargetLowering.cpp | 347 case ISD::SETO: in softenSetCCOperands()
3769 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to in SimplifySetCC()
3771 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
3834 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO in SimplifySetCC()
3836 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
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| H A D | SelectionDAG.cpp | 2024 case ISD::SETO:
2112 case ISD::SETO: return getBoolConstant(R!=APFloat::cmpUnordered, dl, VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 858 case ISD::SETO: in IntCondCCodeToICC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 89 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
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| /third_party/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 637 #define SETO(a) CHOICE(seto a, seto a, seto a) macro
1350 #define SETO(a) seto a macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1970 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \ in CCMaskForCondCode()
1984 case ISD::SETO: return SystemZ::CCMASK_CMP_O; in CCMaskForCondCode()
2799 case ISD::SETO: {
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 3882 case ISD::SETO: return PPC::PRED_NU; in getPredicateForSetCC()
3910 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO in getCRIdxForSetCC()
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| H A D | PPCISelLowering.cpp | 493 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in PPCTargetLowering()
494 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in PPCTargetLowering()
763 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
812 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1844 Op->getOperand(2), ISD::SETO); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsISelLowering.cpp | 622 case ISD::SETO: return Mips::FCOND_OR; in condCodeToFCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 555 case ISD::SETO: in getPTXCmpMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1402 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1577 case ISD::SETO: in changeFPCCToAArch64CC()
1654 case ISD::SETO: in changeVectorFPCCToAArch64CC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1863 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
4683 if (CC == ISD::SETO) { in checkVSELConstraints()
6303 case ISD::SETO: { in LowerVSETCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4921 case ISD::SETO: return X86::COND_NP;
21186 case ISD::SETO: SSECC = 7; break;
21203 case ISD::SETO:
21390 // 1. Get ordered masks from a quiet ISD::SETO
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