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Searched refs:Rt (Results 1 - 25 of 33) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
680 if (Rs >= Rt) { in DecodeAddiGroupBranch()
683 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
694 Rt))); in DecodeAddiGroupBranch()
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
708 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
711 Rt))); in DecodePOP35GroupBranchMMR6()
715 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
720 Rt))); in DecodePOP35GroupBranchMMR6()
725 Rt))); in DecodePOP35GroupBranchMMR6()
749 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeDaddiGroupBranch() local
777 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP37GroupBranchMMR6() local
818 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP65GroupBranchMMR6() local
857 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP75GroupBranchMMR6() local
901 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBlezlGroupBranch() local
946 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBgtzlGroupBranch() local
988 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBgtzGroupBranch() local
1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBlezGroupBranch() local
1093 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeDEXT() local
1135 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeDINS() local
1153 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeCRC() local
2050 unsigned Rt = fieldFromInstruction(Insn, 16, 5); DecodeSpecial3LlSc() local
2560 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodeBgtzGroupBranchMMR6() local
2609 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodeBlezGroupBranchMMR6() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp370 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo in HexagonProcessInstruction()
374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
375 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
376 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
386 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
387 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
392 Rt in HexagonProcessInstruction()
397 MCOperand &Rt = Inst.getOperand(2); HexagonProcessInstruction() local
594 MCOperand &Rt = Inst.getOperand(1); HexagonProcessInstruction() local
[all...]
H A DHexagonBitSimplify.cpp580 case S2_storerf_io: // memh(Rs32+#s11:1)=Rt.H32
581 case S2_pstorerft_io: // if (Pv4) memh(Rs32+#u6:1)=Rt.H32
582 case S2_pstorerff_io: // if (!Pv4) memh(Rs32+#u6:1)=Rt.H32
583 case S4_pstorerftnew_io: // if (Pv4.new) memh(Rs32+#u6:1)=Rt.H32
584 case S4_pstorerffnew_io: // if (!Pv4.new) memh(Rs32+#u6:1)=Rt.H32
585 case S2_storerf_pi: // memh(Rx32++#s4:1)=Rt.H32
586 case S2_pstorerft_pi: // if (Pv4) memh(Rx32++#s4:1)=Rt.H32
587 case S2_pstorerff_pi: // if (!Pv4) memh(Rx32++#s4:1)=Rt.H32
588 case S2_pstorerftnew_pi: // if (Pv4.new) memh(Rx32++#s4:1)=Rt.H32
589 case S2_pstorerffnew_pi: // if (!Pv4.new) memh(Rx32++#s4:1)=Rt
[all...]
H A DHexagonBitTracker.cpp296 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
299 assert(Ws == Rt.width());
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
303 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
/third_party/cmsis/CMSIS/Core/Include/a-profile/
H A Dcmsis_iccarm_a.h255 #define __get_CP64(cp, op1, Rt, CRm) \
256 __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
258 #define __set_CP64(cp, op1, Rt, CRm) \
259 __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
439 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
440 __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
441 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
442 __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
443 #define __get_CP64(cp, op1, Rt, CRm) \
444 __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt)
[all...]
H A Dcmsis_armclang_a.h698 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
699 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
700 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
701 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
H A Dcmsis_gcc_a.h861 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
862 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
863 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
864 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
H A Dcmsis_clang_a.h838 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
839 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
840 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
841 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp200 MCOperand Rs, Rt; in getCompoundInsn() local
210 Rt = L.getOperand(0); in getCompoundInsn()
215 CompoundInsn->addOperand(Rt); in getCompoundInsn()
221 Rt = L.getOperand(0); in getCompoundInsn()
227 CompoundInsn->addOperand(Rt); in getCompoundInsn()
236 Rt = L.getOperand(2); in getCompoundInsn()
242 CompoundInsn->addOperand(Rt); in getCompoundInsn()
249 Rt = L.getOperand(2); in getCompoundInsn()
255 CompoundInsn->addOperand(Rt); in getCompoundInsn()
262 Rt in getCompoundInsn()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.cpp210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt() local
213 Opcode |= Rt << 16; in emitRsRt()
221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16() local
225 Opcode |= Rt << 16; in emitRtRsImm16()
236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel() local
249 Opcode |= Rt << 16; in emitRtRsImm16Rel()
272 const IValueT Rt in emitRdRtSa() local
286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitRdRsRt() local
346 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitCOP1FmtRtFsFd() local
359 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitCOP1MovRtFs() local
668 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui"); lui() local
687 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "ldc1"); ldc1() local
749 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "lwc1"); lwc1() local
823 const IValueT Rt = 0; // $0 move() local
1075 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "sdc1"); sdc1() local
1131 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "swc1"); swc1() local
1158 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "teq"); teq() local
1237 IValueT Rt = encodeGPRegister(OpRt, "Rt", "branch"); emitBr() local
[all...]
H A DIceAssemblerARM32.cpp935 bool IsLoad, bool IsByte, IValueT Rt,
937 assert(Rt < RegARM32::getNumGPRegs());
941 (IsByte ? B : 0) | (Rt << kRdShift) | Address;
946 IValueT Rt, const Operand *OpAddress,
955 // xxx{b}<c> <Rt>, [<Rn>{, #+/-<imm12>}] ; p=1, w=0
956 // xxx{b}<c> <Rt>, [<Rn>], #+/-<imm12> ; p=1, w=1
957 // xxx{b}<c> <Rt>, [<Rn>, #+/-<imm12>]! ; p=0, w=1
959 // cccc010pubwlnnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
973 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
978 // xxx{b}<c> <Rt>, [<R
[all...]
H A DIceAssemblerARM32.h478 // Dm = Rt:Rt2
482 // Qd[Index] = Rt
490 // Rt = Qm[Index]
494 // Rt:Rt2 = Dm
498 // Rt = Sn
512 // Sn = Rt
740 bool IsByte, IValueT Rt, IValueT Address);
748 void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
753 void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt,
758 // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1031 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1041 // Rt is an immediate in prefetch. in DecodeUnsignedLdStInstruction()
1042 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
1052 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1059 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1063 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1067 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1071 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1075 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1079 DecodeFPR8RegisterClass(Inst, Rt, Add in DecodeUnsignedLdStInstruction()
1092 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeSignedLdStInstruction() local
1290 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeExclusiveLdStInstruction() local
1373 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodePairLdStInstruction() local
1753 uint64_t Rt = fieldFromInstruction(insn, 0, 5); DecodeTestAndBranch() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1836 // On stores, the writeback operand precedes Rt. in DecodeAddrMode2IdxInstruction()
1853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1856 // On loads, the writeback operand comes after Rt. in DecodeAddrMode2IdxInstruction()
1887 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1976 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
1985 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
1989 // For {LD,ST}RD, Rt must be even, else undefined. in DecodeAddrMode3Instruction()
1997 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2009 if (writeback && (Rn == 15 || Rn == Rt || R in DecodeAddrMode3Instruction()
3767 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadShift() local
3851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm8() local
3935 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm12() local
4015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadT() local
4053 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadLabel() local
4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LdStPre() local
4751 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeDoubleRegLoad() local
4774 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeDoubleRegStore() local
4799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreImm() local
4824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreReg() local
4851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreImm() local
4876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreReg() local
5447 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVSRR() local
5473 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVRRS() local
5530 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LDRDPreInstruction() local
5567 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2STRDPreInstruction() local
5636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSwap() local
5817 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeLDR() local
5846 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecoderForMRRC2AndMCRR2() local
5903 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeForVMRSandVMSR() local
6422 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVQtoDReg() local
6445 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVDRegtoQ() local
[all...]
/third_party/mesa3d/src/asahi/compiler/
H A Dagx_pack.c506 bool Rt, At, Ot; in agx_pack_instr() local
507 unsigned R = agx_pack_memory_reg(I->dest[0], &Rt); in agx_pack_instr()
535 (((uint64_t) Rt) << 49) | in agx_pack_instr()
550 bool Rt, Ot, Ct, St; in agx_pack_instr() local
553 unsigned R = agx_pack_memory_reg(I->dest[0], &Rt); in agx_pack_instr()
586 (Rt ? (1 << 8) : 0) | in agx_pack_instr()
/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.cc292 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); in cbz()
304 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); in cbnz()
423 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); in tbz()
436 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); in tbnz()
1131 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | in LoadStorePair()
1183 Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | in LoadStorePairNonTemporal()
1380 Emit(LDRSW_x_lit | ImmLLiteral(imm19) | Rt(rt)); in ldrsw()
1387 Emit(op | ImmLLiteral(imm19) | Rt(rt)); in ldr()
1407 Emit(STXRB_w | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(dst.GetBaseRegister())); in stxrb()
1415 Emit(STXRH_w | Rs(rs) | Rt(r in stxrh()
[all...]
H A Dassembler-sve-aarch64.cc3830 Emit(op | mem_op | dtype | Rt(zt) | PgLow8(pg)); in SVELdSt1Helper()
3844 Emit(op | mem_op | msz | num | Rt(zt1) | PgLow8(pg)); in SVELdSt234Helper()
4038 Emit(op | mem_op | msz | u | ff | Rt(zt) | PgLow8(pg)); in SVEScatterGatherHelper()
4148 ImmUnsignedField<21, 16>(imm / divisor) | Rt(zt) | PgLow8(pg)); in SVELd1BroadcastHelper()
4243 Emit(op | Rt(rt) | RnSP(addr.GetScalarBase()) | imm9h | imm9l); in ldr()
4262 Emit(LDFF1B_z_p_bz_d_64_unscaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm)); in ldff1b()
4279 Emit(LDFF1B_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5)); in ldff1b()
4298 Emit(LDFF1D_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm)); in ldff1d()
4312 Emit(LDFF1D_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5)); in ldff1d()
4331 Emit(LDFF1H_z_p_bz_d_64_scaled | Rt(z in ldff1h()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1361 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1364 TmpInst.addOperand(Rt); in processInstruction()
1365 TmpInst.addOperand(Rt); in processInstruction()
1377 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" in processInstruction()
1800 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1801 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1806 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1811 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1820 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1821 unsigned int RegNum = RI->getEncodingValue(Rt in processInstruction()
1843 MCOperand &Rt = Inst.getOperand(2); processInstruction() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
140 Register Reg = Rs == GAReg ? Rt : Rs; in matchLargeOffset()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc705 bool result = instr->IsLdrLiteralX() && (instr->Rt() == kZeroRegCode); in IsConstantPoolAt()
791 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); in cbz()
799 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); in cbnz()
808 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); in tbz()
817 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); in tbnz()
1251 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
1314 Emit(LoadLiteralOpFor(rt) | ImmLLiteral(imm19) | Rt(rt)); in ldr_pcrel()
1356 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); in ldar()
1362 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); in ldaxr()
1368 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(r in stlr()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3374 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3376 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3381 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3383 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3411 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3415 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3423 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3425 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3446 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt()
3447 if (Rt in getNumMicroOpsSwiftLdSt()
3461 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3487 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3497 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3534 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
[all...]
H A DThumb2SizeReduction.cpp467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
472 assert(isARMLowRegister(Rt)); in ReduceLoadStore()
485 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3966 // the Rt == Rt2. All of those are undefined behaviour. in validateInstruction()
3973 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
3976 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
3990 unsigned Rt = Inst.getOperand(0).getReg(); in validateInstruction() local
3992 if (Rt == Rt2) in validateInstruction()
3993 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); in validateInstruction()
4003 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4005 if (Rt == Rt2) in validateInstruction()
4006 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); in validateInstruction()
4019 unsigned Rt in validateInstruction() local
4052 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
4071 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
4087 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
[all...]
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1756 bool take_branch = ((xreg(instr->Rt()) & (1ULL << bit_pos)) == 0);
1772 unsigned rt = instr->Rt();
1992 unsigned srcdst = instr->Rt();
2155 unsigned rt = instr->Rt();
2313 unsigned rt = instr->Rt();
2389 unsigned rt = instr->Rt();
3358 set_xreg(instr->Rt(), nzcv().RawValue());
3361 set_xreg(instr->Rt(), fpcr().RawValue());
3371 nzcv().SetRawValue(wreg(instr->Rt()));
3375 fpcr().SetRawValue(wreg(instr->Rt()));
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3516 Register Rt = MI.getOperand(1).getReg(); in emitST_F16_PSEUDO() local
3541 .addReg(Rt) in emitST_F16_PSEUDO()
3581 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() local
3584 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt); in emitLD_F16_PSEUDO()
3590 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32); in emitLD_F16_PSEUDO()
3591 Rt = Tmp; in emitLD_F16_PSEUDO()
3594 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt); in emitLD_F16_PSEUDO()

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