| /third_party/node/deps/v8/src/wasm/ |
| H A D | wasm-opcodes-inl.h | 114 CASE_INT_OP(Ror, "ror") in OpcodeName()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3550 COMPARE_T32(Ror(eq, r7, r7, r3), in TEST()
3554 COMPARE_T32(Ror(eq, r8, r8, r3), in TEST()
3558 COMPARE_T32(Ror(eq, r0, r1, 16), in TEST()
4177 CHECK_T32_16(Ror(DontCare, r0, r0, r1), "rors r0, r1\n"); in TEST()
4179 CHECK_T32_16_IT_BLOCK(Ror(DontCare, eq, r0, r0, r1), in TEST()
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 148 M(Ror) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 148 M(Ror) \
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| H A D | test-assembler-aarch32.cc | 786 __ Ror(r6, r1, 20); in TEST()
816 __ Ror(r6, r1, r9); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 883 void TurboAssembler::Ror(const Register& rd, const Register& rs, in Ror() function in v8::internal::TurboAssembler
890 void TurboAssembler::Ror(const Register& rd, const Register& rn, in Ror() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1062 inline void Ror(const Register& rd, const Register& rs, unsigned shift);
1063 inline void Ror(const Register& rd, const Register& rn, const Register& rm);
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.h | 1010 void Ror(Register rd, Register rm, const Operand &shift_imm,
1012 void Ror(Register rd, Register rm, Register rs, Condition cond = AL);
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| H A D | assembler_arm.cc | 2505 void Assembler::Ror(Register rd, Register rm, const Operand &shift_imm,
2512 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 6737 __ Ror(x16, x0, x1);
6738 __ Ror(x17, x0, x2);
6739 __ Ror(x18, x0, x3);
6740 __ Ror(x19, x0, x4);
6741 __ Ror(x20, x0, x5);
6742 __ Ror(x21, x0, x6);
6744 __ Ror(w22, w0, w1);
6745 __ Ror(w23, w0, w2);
6746 __ Ror(w24, w0, w3);
6747 __ Ror(w2
[all...] |
| H A D | test-assembler-neon-aarch64.cc | 10992 __ Ror(x0, x0, 8); in TEST()
10994 __ Ror(x0, x0, 8); in TEST()
10996 __ Ror(x0, x0, 8); in TEST()
11138 __ Ror(x0, x0, 8); in TEST()
11140 __ Ror(x0, x0, 8); in TEST()
11142 __ Ror(x0, x0, 8); in TEST()
11475 __ Ror(x0, x0, 8); in TEST()
11477 __ Ror(x0, x0, 8); in TEST()
11479 __ Ror(x0, x0, 8); in TEST()
11840 __ Ror(x in TEST()
[all...] |
| /third_party/node/deps/v8/src/compiler/ |
| H A D | machine-operator.h | 1053 V(Word, Ror) \
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | macro-assembler-mips.cc | 879 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
1729 Ror(dest, dest, pos); in CallRecordWriteStub()
1735 Ror(dest, dest, scratch); in CallRecordWriteStub()
2596 Ror(rd, rs, 16); in CallRecordWriteStub()
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| H A D | macro-assembler-mips.h | 464 DEFINE_INSTRUCTION(Ror)
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | macro-assembler-mips64.h | 478 DEFINE_INSTRUCTION(Ror)
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| H A D | macro-assembler-mips64.cc | 1012 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | macro-assembler-riscv64.h | 474 DEFINE_INSTRUCTION(Ror)
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| H A D | macro-assembler-riscv64.cc | 961 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { in Ror() function in v8::internal::TurboAssembler
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3678 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3696 void Ror(Register rd, Register rm, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3697 Ror(al, rd, rm, operand); in MacroAssembler()
3699 void Ror(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
3706 Ror(cond, rd, rm, operand); in MacroAssembler()
3718 Ror(cond, rd, rm, operand); in MacroAssembler()
3723 void Ror(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
3727 Ror(flags, al, rd, rm, operand); in MacroAssembler()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1437 ASSEMBLE_SHIFT(Ror, 64); in AssembleArchInstruction()
1440 ASSEMBLE_SHIFT(Ror, 32); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2386 void Ror(const Register& rd, const Register& rs, unsigned shift) { in Ror() function in vixl::aarch64::MacroAssembler
2393 void Ror(const Register& rd, const Register& rn, const Register& rm) { in Ror() function in vixl::aarch64::MacroAssembler
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 1186 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 1133 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | code-generator-riscv64.cc | 1175 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
|