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Searched refs:Rn (Results 1 - 22 of 22) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dassembler-sve-aarch64.cc82 Emit(op | msz | Rd(zd) | Rn(addr.GetVectorBase()) | in adr()
136 Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in and_()
145 Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in bic()
154 Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in eor()
163 Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in orr()
214 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in asr()
249 Emit(ASRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in asrr()
289 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in lsl()
306 Emit(LSLR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in lslr()
346 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(z in lsr()
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H A Dassembler-aarch64.cc183 Emit(BR | Rn(xn)); in br()
189 Emit(BLR | Rn(xn)); in blr()
195 Emit(RET | Rn(xn)); in ret()
202 Emit(BRAAZ | Rn(xn) | Rd_mask); in braaz()
208 Emit(BRABZ | Rn(xn) | Rd_mask); in brabz()
214 Emit(BLRAAZ | Rn(xn) | Rd_mask); in blraaz()
220 Emit(BLRABZ | Rn(xn) | Rd_mask); in blrabz()
237 Emit(BRAA | Rn(xn) | RdSP(xm)); in braa()
243 Emit(BRAB | Rn(xn) | RdSP(xm)); in brab()
249 Emit(BLRAA | Rn(x in blraa()
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H A Dconstants-aarch64.h77 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1558 // Writeback not allowed if Rn is in the target list. in DecodeRegListOperand()
1652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
1827 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
1846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1887 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1932 unsigned Rn in DecodeSORegMemOperand() local
1977 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeAddrMode3Instruction() local
2167 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeRFEInstruction() local
2198 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeQADDInstruction() local
2220 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeMemMultipleWritebackInstruction() local
2474 unsigned Rn = fieldFromInstruction(Insn, 0, 4); DecodeSMLAInstruction() local
2502 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeTSTInstruction() local
2552 unsigned Rn = fieldFromInstruction(Val, 13, 4); DecodeAddrModeImm12Operand() local
2570 unsigned Rn = fieldFromInstruction(Val, 9, 4); DecodeAddrMode5Operand() local
2590 unsigned Rn = fieldFromInstruction(Val, 9, 4); DecodeAddrMode5FP16Operand() local
2688 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLDInstruction() local
3015 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVSTInstruction() local
3284 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD1DupInstruction() local
3331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD2DupInstruction() local
3379 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD3DupInstruction() local
3414 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD4DupInstruction() local
3609 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeTBLInstruction() local
3691 unsigned Rn = fieldFromInstruction(Val, 0, 3); DecodeThumbAddrModeRR() local
3706 unsigned Rn = fieldFromInstruction(Val, 0, 3); DecodeThumbAddrModeIS() local
3738 unsigned Rn = fieldFromInstruction(Val, 6, 4); DecodeT2AddrModeSOReg() local
3768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LoadShift() local
3850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LoadImm8() local
3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LoadImm12() local
4014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LoadT() local
4135 unsigned Rn = fieldFromInstruction(Val, 9, 4); DecodeT2AddrModeImm8s4() local
4151 unsigned Rn = fieldFromInstruction(Val, 8, 4); DecodeT2AddrModeImm7s4() local
4166 unsigned Rn = fieldFromInstruction(Val, 8, 4); DecodeT2AddrModeImm0_1020s4() local
4208 unsigned Rn = fieldFromInstruction(Val, 9, 4); DecodeT2AddrModeImm8() local
4256 unsigned Rn = fieldFromInstruction(Val, 8, 3); DecodeTAddrModeImm7() local
4273 unsigned Rn = fieldFromInstruction(Val, 8, 4); DecodeT2AddrModeImm7() local
4291 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LdStPre() local
4351 unsigned Rn = fieldFromInstruction(Val, 13, 4); DecodeT2AddrModeImm12() local
4436 unsigned Rn = fieldFromInstruction(Insn, 3, 4); DecodeMveAddrModeRQ() local
4514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeThumbTableBranch() local
4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeDoubleRegLoad() local
4775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeDoubleRegStore() local
4798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeLDRPreImm() local
4823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeLDRPreReg() local
4850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeSTRPreImm() local
4875 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeSTRPreReg() local
4900 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD1LN() local
4967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVST1LN() local
5032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD2LN() local
5099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVST2LN() local
5162 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD3LN() local
5232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVST3LN() local
5295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVLD4LN() local
5376 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeVST4LN() local
5532 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2LDRDPreInstruction() local
5569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2STRDPreInstruction() local
5638 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeSwap() local
5816 unsigned Rn = fieldFromInstruction(Val, 16, 4); DecodeLDR() local
6014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeLOLoop() local
6322 unsigned Rn = fieldFromInstruction(Val, 16, 4); DecodeVSTRVLDR_SYSREG() local
6339 DecodeMVE_MEM_pre( MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) DecodeMVE_MEM_pre() argument
6607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeMveVCTP() local
6624 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); DecodeT2AddSubSPImm() local
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp135 IValueT encodeGPRRegister(RegARM32::GPRRegister Rn) { in encodeGPRRegister() argument
136 return static_cast<IValueT>(Rn); in encodeGPRRegister()
283 // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
285 // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
289 // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
291 // Rn.
295 // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
297 // Rn should be used, and iiiiiiiiiiii defines the immediate 12-bit value.
301 // Value=000000001000nnnn0000000000000000 where nnnn=Rn.
304 // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
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H A DIceAssemblerARM32.h260 // Note: Registers is a bitset, where bit n corresponds to register Rn.
265 // Note: Registers is a bitset, where bit n corresponds to register Rn.
715 // s=SetFlags, oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM
718 bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12,
727 // Same as above, but the value for Rd and Rn have already been converted
758 // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt.
782 // Pattern 111100000D00nnnnddddttttssaammmm | Opcode where Ddddd=Dd, nnnn=Rn,
785 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
789 // Pattern 111100000D00nnnnddddss00aaaammmm | Opcode where Ddddd=Dd, nnnn=Rn,
791 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValue
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp846 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
851 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
854 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
937 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
965 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
986 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1032 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
1083 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1093 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
1151 DecodeGPR64spRegisterClass(Inst, Rn, Add in DecodeSignedLdStInstruction()
1291 unsigned Rn = fieldFromInstruction(insn, 5, 5); DecodeExclusiveLdStInstruction() local
1374 unsigned Rn = fieldFromInstruction(insn, 5, 5); DecodePairLdStInstruction() local
1508 unsigned Rn = fieldFromInstruction(insn, 5, 5); DecodeAddSubERegInstruction() local
1565 unsigned Rn = fieldFromInstruction(insn, 5, 5); DecodeLogicalImmInstruction() local
1671 unsigned Rn = fieldFromInstruction(insn, 5, 5); DecodeAddSubImmShift() local
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc710 instr->following()->Rn() == kZeroRegCode)); in IsConstantPoolAt()
743 Emit(BLR | Rn(xzr)); in EmitPoolGuard()
758 Emit(BR | Rn(xn)); in br()
766 Emit(BLR | Rn(xn)); in blr()
771 Emit(RET | Rn(xn)); in ret()
957 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
964 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
971 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
978 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
987 ImmS(imms, rn.SizeInBits()) | Rn(r in bfm()
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H A Dconstants-arm64.h154 V_(Rn, 9, 5, Bits) /* First source register. */ \
H A Dassembler-arm64.h2112 static Instr Rn(CPURegister rn) {
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1088 new_val = AddWithCarry<T>(instr->FlagsUpdate(), reg<T>(instr->Rn()), op2, in AddSubWithCarry()
1170 T op1 = reg<T>(instr->Rn());
1723 if (!PcIsInGuardedPage() || (instr->Rn() == 16) || (instr->Rn() == 17)) {
1732 Instruction* target = reg<Instruction*>(instr->Rn());
1736 if (instr->Rn() == 31) {
1808 AddWithCarry<T>(set_flags, reg<T>(instr->Rn(), instr->RnMode()), op2);
1813 new_val = AddWithCarry<T>(set_flags, reg<T>(instr->Rn(), instr->RnMode()),
1891 T op1 = reg<T>(instr->Rn());
1946 T op1 = reg<T>(instr->Rn());
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp933 // [Rn, Rm] in getThumbAddrModeRegRegOpValue()
935 // {2-0} = Rn in getThumbAddrModeRegRegOpValue()
938 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
940 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
991 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue()
1065 // {6-3} Rn in getMveAddrModeRQOpValue()
1070 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue() local
1075 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1124 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1256 unsigned Rn
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/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.h59 return (instr->Rn() == kZeroRegCode); in RnIsZROrSP()
H A Ddisasm-arm64.cc100 const char* form = "'Rd, 'Rn, 'Rm'NDP"; in VisitAddSubShifted()
101 const char* form_cmp = "'Rn, 'Rm'NDP"; in VisitAddSubShifted()
190 const char* form = "'Rd, 'Rn, 'Rm"; in VisitAddSubWithCarry()
230 const char* form = "'Rds, 'Rn, 'ITri"; in VisitLogicalImmediate()
263 form = "'Rn, 'ITri"; in VisitLogicalImmediate()
304 const char* form = "'Rd, 'Rn, 'Rm'NLo"; in VisitLogicalShifted()
332 form = "'Rn, 'Rm'NLo"; in VisitLogicalShifted()
363 const char* form = "'Rn, 'Rm, 'INzcv, 'Cond"; in VisitConditionalCompareRegister()
383 const char* form = "'Rn, 'IP, 'INzcv, 'Cond"; in VisitConditionalCompareImmediate()
402 bool rn_is_rm = (instr->Rn() in VisitConditionalSelect()
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/third_party/ffmpeg/libavcodec/arm/
H A Dhpeldsp_arm.S53 @ Rd = (Rn | Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
55 @ Rn = destroy
67 @ Rd = (Rn & Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
69 @ Rn = destroy
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc92 void FormatNeonMemory(int Rn, int align, int Rm);
296 if (format[1] == 'n') { // 'rn: Rn register in FormatRegister()
403 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
405 converter_.NameOfCPURegister(Rn)); in FormatNeonMemory()
744 // Rn field to encode it. in DecodeType01()
749 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
750 // Rn field to encode the Rd register and the Rd field to encode in DecodeType01()
751 // the Rn register. in DecodeType01()
755 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
756 // Rn fiel in DecodeType01()
2458 int Rn = instr->VnValue(); DecodeAdvancedSIMDElementOrStructureLoadStore() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
473 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
481 .addReg(Rn, RegState::Define) in ReduceLoadStore()
482 .addReg(Rn) in ReduceLoadStore()
H A DARMBaseInstrInfo.cpp3462 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
3467 return (Rt == Rn) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3488 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3493 return (Rt == Rn) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3498 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3499 return (Rt == Rn) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3535 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
3536 return (Rt == Rn) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3794 // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops in getLDMVariableDefsSize()
3795 // (outs GPR:$wb), (ins GPR:$Rn, in getLDMVariableDefsSize()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3975 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
3976 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
3979 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4021 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
4022 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4025 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4053 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
4054 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4072 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
4073 if (RI->isSubRegisterEq(Rn, R in validateInstruction()
4088 unsigned Rn = Inst.getOperand(2).getReg(); validateInstruction() local
4102 unsigned Rn = Inst.getOperand(3).getReg(); validateInstruction() local
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/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.cc85 void Simulator::AdvancedSIMDElementOrStructureLoadStoreWriteback(int Rn, int Rm, in AdvancedSIMDElementOrStructureLoadStoreWriteback() argument
89 set_register(Rn, get_register(Rn) + ebytes); in AdvancedSIMDElementOrStructureLoadStoreWriteback()
91 set_register(Rn, get_register(Rn) + get_register(Rm)); in AdvancedSIMDElementOrStructureLoadStoreWriteback()
2046 // Rn field to encode it. in DecodeType01()
2059 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
2060 // Rn field to encode the Rd register and the Rd field to encode in DecodeType01()
2061 // the Rn register. in DecodeType01()
2075 // when referring to the target registers. They are mapped to the Rn in DecodeType01()
5763 int Rn = instr->VnValue(); DecodeAdvancedSIMDLoadStoreMultipleStructures() local
5816 int Rn = instr->VnValue(); DecodeAdvancedSIMDLoadSingleStructureToAllLanes() local
5865 int Rn = instr->VnValue(); DecodeAdvancedSIMDLoadStoreSingleStructureToOneLane() local
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H A Dsimulator-arm.h339 void AdvancedSIMDElementOrStructureLoadStoreWriteback(int Rn, int Rm,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5555 // If we have a three-operand form, make sure to set Rn to be the operand in cvtThumbMultiply()
7290 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateLDRDSTRD() local
7292 if (Rn == Rt || Rn == Rt2) { in validateLDRDSTRD()
7479 // Rt must be different from Rn. in validateInstruction()
7481 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
7483 if (Rt == Rn) in validateInstruction()
7512 // Rt must be different from Rn. in validateInstruction()
7514 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
7516 if (Rt == Rn) in validateInstruction()
7589 unsigned Rn = Inst.getOperand(0).getReg(); validateInstruction() local
9935 unsigned Rn = Inst.getOperand(0).getReg(); processInstruction() local
9959 unsigned Rn = Inst.getOperand(0).getReg(); processInstruction() local
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