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Searched refs:Regs (Results 1 - 25 of 65) sorted by relevance

123

/third_party/backends/backend/
H A Dhp3900_rts8822.c82 void shadingtest1 (struct st_device *dev, SANE_Byte * Regs,
84 static SANE_Int Calib_test (struct st_device *dev, SANE_Byte * Regs,
88 SANE_Byte * Regs,
167 static SANE_Int RTS_Enable_CCD (struct st_device *dev, SANE_Byte * Regs,
172 static SANE_Int RTS_DMA_CheckType (struct st_device *dev, SANE_Byte * Regs);
181 static SANE_Int RTS_DMA_SetType (struct st_device *dev, SANE_Byte * Regs,
207 static SANE_Byte RTS_IsExecuting (struct st_device *dev, SANE_Byte * Regs);
211 static SANE_Int RTS_GetImage (struct st_device *dev, SANE_Byte * Regs,
239 static SANE_Int RTS_Setup (struct st_device *dev, SANE_Byte * Regs,
246 static void RTS_Setup_Channels (struct st_device *dev, SANE_Byte * Regs,
765 SetLock(USB_Handle usb_handle, SANE_Byte * Regs, SANE_Byte Enable) SetLock() argument
1636 SetScanParams(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_hwdconfig *hwdcfg) SetScanParams() argument
2533 SANE_Byte *Regs; Lamp_PWM_DutyCycle_Set() local
2573 SANE_Byte *Regs; Head_ParkHome() local
2654 Motor_Move(struct st_device *dev, SANE_Byte * Regs, struct st_motormove *mymotor, struct st_motorpos *mtrpos) Motor_Move() argument
3011 Motor_Setup_Steps(struct st_device *dev, SANE_Byte * Regs, SANE_Int mysetting) Motor_Setup_Steps() argument
3528 RTS_Setup_RefVoltages(struct st_device *dev, SANE_Byte * Regs) RTS_Setup_RefVoltages() argument
3805 Head_IsAtHome(struct st_device *dev, SANE_Byte * Regs) Head_IsAtHome() argument
3832 RTS_IsExecuting(struct st_device *dev, SANE_Byte * Regs) RTS_IsExecuting() argument
3884 RTS_Enable_CCD(struct st_device *dev, SANE_Byte * Regs, SANE_Int channels) RTS_Enable_CCD() argument
4359 RTS_DMA_CheckType(struct st_device *dev, SANE_Byte * Regs) RTS_DMA_CheckType() argument
4533 RTS_DMA_SetType(struct st_device *dev, SANE_Byte * Regs, SANE_Byte ramtype) RTS_DMA_SetType() argument
4712 Gamma_Apply(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_hwdconfig *hwdcfg, struct st_gammatables *mygamma) Gamma_Apply() argument
5028 Timing_SetLinearImageSensorClock(SANE_Byte * Regs, struct st_cph *cph) Timing_SetLinearImageSensorClock() argument
5066 RTS_Setup_SensorTiming(struct st_device *dev, SANE_Int mytiming, SANE_Byte * Regs) RTS_Setup_SensorTiming() argument
5163 SetMultiExposure(struct st_device *dev, SANE_Byte * Regs) SetMultiExposure() argument
5416 Lamp_SetGainMode(struct st_device *dev, SANE_Byte * Regs, SANE_Int resolution, SANE_Byte gainmode) Lamp_SetGainMode() argument
6196 Gamma_SendTables(struct st_device *dev, SANE_Byte * Regs, SANE_Byte * gammatable, SANE_Int size) Gamma_SendTables() argument
7957 Lamp_Warmup(struct st_device *dev, SANE_Byte * Regs, SANE_Int lamp, SANE_Int resolution) Lamp_Warmup() argument
8061 SANE_Byte Regs[RT_BUFFER_LEN], mlock; Scan_Start() local
8452 RTS_Setup_Motor(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, SANE_Int somevalue) RTS_Setup_Motor() argument
8627 RTS_Setup_Exposure_Times(SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_scanmode *sm) RTS_Setup_Exposure_Times() argument
8678 RTS_Setup_Line_Distances(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_hwdconfig *hwdcfg, SANE_Int mycolormode, SANE_Int arrangeline) RTS_Setup_Line_Distances() argument
8762 RTS_Setup_Depth(SANE_Byte * Regs, struct st_scanparams *scancfg, SANE_Int mycolormode) RTS_Setup_Depth() argument
8812 RTS_Setup_Shading(SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_hwdconfig *hwdcfg, SANE_Int bytes_per_line) RTS_Setup_Shading() argument
8948 RTS_Setup_Channels(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, SANE_Int mycolormode) RTS_Setup_Channels() argument
9041 RTS_Setup(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_hwdconfig *hwdcfg, struct st_gain_offset *gain_offset) RTS_Setup() argument
9229 RTS_Setup_Coords(SANE_Byte * Regs, SANE_Int iLeft, SANE_Int iTop, SANE_Int width, SANE_Int height) RTS_Setup_Coords() argument
9255 RTS_Setup_GainOffset(SANE_Byte * Regs, struct st_gain_offset *gain_offset) RTS_Setup_GainOffset() argument
9334 Calibrate_Malloc(struct st_cal2 *calbuffers, SANE_Byte * Regs, struct st_calibration *myCalib, SANE_Int somelength) Calibrate_Malloc() argument
9536 fn3330(struct st_device *dev, SANE_Byte * Regs, struct st_cal2 *calbuffers, SANE_Int sensorchannelcolor, SANE_Int * tablepos, SANE_Int data) fn3330() argument
9680 fn3730(struct st_device *dev, struct st_cal2 *calbuffers, SANE_Byte * Regs, USHORT * table, SANE_Int sensorchannelcolor, SANE_Int data) fn3730() argument
9706 Shading_white_apply(struct st_device *dev, SANE_Byte * Regs, SANE_Int channels, struct st_calibration *myCalib, struct st_cal2 *calbuffers) Shading_white_apply() argument
9768 Shading_black_apply(struct st_device *dev, SANE_Byte * Regs, SANE_Int channels, struct st_calibration *myCalib, struct st_cal2 *calbuffers) Shading_black_apply() argument
9832 Shading_apply(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *myvar, struct st_calibration *myCalib) Shading_apply() argument
10306 RTS_GetImage(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_gain_offset *gain_offset, SANE_Byte * buffer, struct st_calibration *myCalib, SANE_Int options, SANE_Int gaincontrol) RTS_GetImage() argument
10533 Refs_Detect(struct st_device *dev, SANE_Byte * Regs, SANE_Int resolution_x, SANE_Int resolution_y, SANE_Int * x, SANE_Int * y) Refs_Detect() argument
10647 Refs_Set(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg) Refs_Set() argument
10738 Lamp_Status_Set(struct st_device *dev, SANE_Byte * Regs, SANE_Int turn_on, SANE_Int lamp) Lamp_Status_Set() argument
10976 SANE_Byte *Regs, *image; GetOneLineInfo() local
11279 SANE_Byte *Regs; Head_Relocate() local
11905 SANE_Byte *Regs; Calib_PAGain() local
12161 SANE_Byte Regs[RT_BUFFER_LEN]; /*f1c4 */ Calib_AdcOffsetRT() local
13612 Calibration(struct st_device *dev, SANE_Byte * Regs, struct st_scanparams *scancfg, struct st_calibration *myCalib, SANE_Int value) Calibration() argument
14032 RTS_Setup_Gamma(SANE_Byte * Regs, struct st_hwdconfig *hwdcfg) RTS_Setup_Gamma() argument
14451 WShading_Calibrate(struct st_device *dev, SANE_Byte * Regs, struct st_calibration *myCalib, struct st_scanparams *scancfg) WShading_Calibrate() argument
14674 motor_pos(struct st_device *dev, SANE_Byte * Regs, struct st_calibration *myCalib, struct st_scanparams *scancfg) motor_pos() argument
14806 Calib_BlackShading_jkd(struct st_device *dev, SANE_Byte * Regs, struct st_calibration *myCalib, struct st_scanparams *scancfg) Calib_BlackShading_jkd() argument
14942 Calib_test(struct st_device *dev, SANE_Byte * Regs, struct st_calibration *myCalib, struct st_scanparams *scancfg) Calib_test() argument
15070 shadingtest1(struct st_device *dev, SANE_Byte * Regs, struct st_calibration *myCalib) shadingtest1() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h343 /// in the set, or Regs.size() if they are all allocated.
344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
345 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
346 if (!isAllocated(Regs[i])) in getFirstUnallocated()
348 return Regs.size(); in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
372 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
373 if (FirstUnalloc == Regs.size()) in AllocateReg()
377 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument
412 AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) AllocateReg() argument
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H A DRegisterPressure.h275 RegSet Regs;
297 RegSet::const_iterator I = Regs.find(SparseIndex);
298 if (I == Regs.end())
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
320 RegSet::iterator I = Regs.find(SparseIndex);
321 if (I == Regs.end())
329 return Regs.size();
334 for (const IndexMaskPair &P : Regs) {
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
85 RegNo = Regs[RegNo]; in decodeRegisterClass()
292 const unsigned *Regs) {
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
302 const unsigned *Regs) {
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
312 const unsigned *Regs) {
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
324 const unsigned *Regs) {
82 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size) decodeRegisterClass() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86CallLowering.cpp64 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); in splitToValueTypes()
74 SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), in splitToValueTypes()
89 SplitRegs.push_back(Info.Regs[0]); in splitToValueTypes()
212 [&](ArrayRef<Register> Regs) { in lowerReturn()
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
414 if (OrigArg.Regs.size() > 1) in lowerCall()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
419 MIRBuilder.buildUnmerge(Regs, OrigAr in lowerCall()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h47 SmallVector<Register, 4> Regs; member
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty, in ArgInfo()
59 : Regs(Regs.begin(), Regs.end()), Ty(Ty), in ArgInfo()
61 if (!Regs.empty() && Flags.empty()) in ArgInfo()
64 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) && in ArgInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp142 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); in packRegs()
165 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch"); in unpackRegs()
228 Args[i].OrigRegs.push_back(Args[i].Regs[0]); in handleAssignments()
229 Args[i].Regs.clear(); in handleAssignments()
246 Args[i].Regs.push_back(Reg); in handleAssignments()
262 Register LargeReg = Args[i].Regs[0]; in handleAssignments()
268 Args[i].Regs.clear(); in handleAssignments()
279 Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); in handleAssignments()
301 Register ArgReg = Args[i].Regs[0]; in handleAssignments()
309 unsigned NumArgRegs = Args[i].Regs in handleAssignments()
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H A DIRTranslator.cpp164 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
170 Regs->push_back(0); in allocateVRegs()
171 return *Regs; in allocateVRegs()
870 ArrayRef<Register> Regs = getOrCreateVRegs(LI); in translateLoad()
878 assert(Regs.size() == 1 && "swifterror should be single pointer"); in translateLoad()
881 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
886 Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr; in translateLoad()
887 for (unsigned i = 0; i < Regs.size(); ++i) { in translateLoad()
896 Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8, in translateLoad()
899 MIRBuilder.buildLoad(Regs[ in translateLoad()
1032 auto &Regs = *VMap.getVRegs(U); translateBitCast() local
1879 auto &Regs = *VMap.getVRegs(U); translateInsertElement() local
1903 auto &Regs = *VMap.getVRegs(U); translateExtractElement() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
108 while (Regs) {
110 auto RangeMSB = 32 - countLeadingZeros(Regs);
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
121 Regs &= ~(-1u << RangeLSB);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp166 assert(OrigArg.Regs.size() == SplitVTs.size()); in splitToValueTypes()
178 SplitArgs.emplace_back(OrigArg.Regs[SplitIdx], Ty, in splitToValueTypes()
281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerReturnVal()
282 unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); in lowerReturnVal()
491 ArrayRef<Register> Regs, in packSplitRegsToOrigType()
495 B.buildMerge(OrigRegs[0], Regs); in packSplitRegsToOrigType()
505 B.buildConcatVectors(OrigRegs[0], Regs); in packSplitRegsToOrigType()
512 auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs); in packSplitRegsToOrigType()
535 for (Register Reg : Regs) in packSplitRegsToOrigType()
539 B.buildBuildVector(OrigRegs[0], Regs); in packSplitRegsToOrigType()
489 packSplitRegsToOrigType(MachineIRBuilder &B, ArrayRef<Register> OrigRegs, ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) packSplitRegsToOrigType() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/
H A DHWEventListener.h74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
97 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp85 std::vector<unsigned> &Regs, in GetGroupRegs()
90 Regs.push_back(Reg); in GetGroupRegs()
562 std::vector<unsigned> Regs;
563 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
564 assert(!Regs.empty() && "Empty register group!");
565 if (Regs.empty())
575 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
576 unsigned Reg = Regs[i];
598 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
599 unsigned Reg = Regs[
83 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) GetGroupRegs() argument
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H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs;
341 auto I = partition_point(Regs, [&](int I) {
344 Regs.insert(I, rx);
350 while (!Regs.empty()) {
352 dv = LiveRegs[Regs.pop_back_val()];
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp161 auto Regs = getRegisters(); in getRegister() local
162 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
163 if (It == Regs.end()) in getRegister()
555 auto Regs = getRegisters(); in toString() local
556 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
557 if (I != Regs.begin()) in toString()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DRDFRegisters.cpp324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
327 Regs.set(*S); in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef()
335 AliasedRegs(U, Regs); in makeRegRef()
343 Regs &= AR; in makeRegRef()
351 int F = Regs.find_first(); in makeRegRef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp142 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
200 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
207 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
230 Register PartReg = OrigArg.Regs[i]; in splitToValueTypes()
366 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
H A DARMFrameLowering.cpp986 SmallVector<RegAndKill, 4> Regs; in emitPushInst()
1013 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn)); in emitPushInst()
1016 if (Regs.empty()) in emitPushInst()
1019 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { in emitPushInst()
1023 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
1028 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
1029 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
1030 } else if (Regs.size() == 1) { in emitPushInst()
1032 .addReg(Regs[ in emitPushInst()
1074 SmallVector<unsigned, 4> Regs; emitPopInst() local
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H A DARMLoadStoreOptimizer.cpp176 ArrayRef<std::pair<unsigned, bool>> Regs,
182 ArrayRef<std::pair<unsigned, bool>> Regs,
580 /// Return the first register of class \p RegClass that is not in \p Regs.
612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg() argument
614 for (const std::pair<unsigned, bool> &R : Regs) in ContainsReg()
621 /// Regs as the register operands that would be loaded / stored. It returns
627 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti()
629 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
643 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
683 NewBase = Regs[NumReg in CreateLoadStoreMulti()
623 CreateLoadStoreMulti( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) CreateLoadStoreMulti() argument
830 CreateLoadStoreDouble( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) const CreateLoadStoreDouble() argument
860 SmallVector<std::pair<unsigned, bool>, 8> Regs; MergeOpsUpdate() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
414 RegisterGroup Group, const unsigned *Regs,
427 MemoryKind MemKind, const unsigned *Regs,
735 // Parse a register of group Group. If Regs is nonnull, use it to map
742 const unsigned *Regs, bool IsAddress) { in parseRegister()
747 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
751 if (Regs) in parseRegister()
752 Reg.Num = Regs[Reg.Num]; in parseRegister()
759 const unsigned *Regs, RegisterKin in parseRegister()
741 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) parseRegister() argument
758 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) parseRegister() argument
896 parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) parseAddress() argument
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/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-register.h353 typename... Regs,
355 std::is_same<Register, Regs>, std::is_same<DoubleRegister, Regs>,
356 std::is_same<LiftoffRegister, Regs>>...>>>
357 constexpr LiftoffRegList(Regs... regs) { in LiftoffRegList()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
390 for (unsigned i = 0; Regs[i]; ++i) in determineCalleeSaves()
391 if (RISCV::FPR32RegClass.contains(Regs[i]) || in determineCalleeSaves()
392 RISCV::FPR64RegClass.contains(Regs[i])) in determineCalleeSaves()
393 SavedRegs.set(Regs[i]); in determineCalleeSaves()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() argument
1123 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() argument
1132 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() argument
1140 if (Regs.size() == 1) in createTuple()
1141 return Regs[0]; in createTuple()
1143 assert(Regs.size() >= 2 && Regs.size() <= 4); in createTuple()
1145 SDLoc DL(Regs[ in createTuple()
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/third_party/mesa3d/include/android_stub/backtrace/
H A DBacktrace.h103 class Regs;
134 static bool Unwind(unwindstack::Regs* regs, BacktraceMap* back_map,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.cpp135 static const unsigned Regs[2][2] = { in getFrameRegister() local
140 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()]; in getFrameRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h850 SmallVector<unsigned, 4> Regs; member
874 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); in append()
875 RegCount.push_back(RHS.Regs.size()); in append()

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