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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
42 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
199 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
202 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
203 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
215 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList in CC_ARM_AAPCS_Custom_Aggregate()
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H A DThumb2ITBlockPass.cpp83 using RegList = SmallVector<unsigned, 4>; in TrackDefUses()
84 RegList LocalDefs; in TrackDefUses()
85 RegList LocalUses; in TrackDefUses()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in TrackDefUses()
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-assembler-defs.h18 constexpr RegList kLiftoffAssemblerGpCacheRegs = {eax, ecx, edx, esi, edi};
26 constexpr RegList kLiftoffAssemblerGpCacheRegs = {rax, rcx, rdx, rbx,
34 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, t0, t1, t2,
42 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
51 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
63 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r0, r1, r2, r3, r4,
74 constexpr RegList kLiftoffAssemblerGpCacheRegs = {
85 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r2, r3, r4, r5,
93 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r3, r4, r5, r6, r7,
103 constexpr RegList kLiftoffAssemblerGpCacheReg
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/third_party/node/deps/v8/src/codegen/arm/
H A Dreglist-arm.h14 using RegList = RegListBase<Register>;
16 ASSERT_TRIVIALLY_COPYABLE(RegList);
23 const RegList kJSCallerSaved = {r0, // r0 a1
31 const RegList kCalleeSaved = {r4, // r4 v1
42 const RegList kCallerSaved = {r0, // r0
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp90 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
92 RegList = XRegList; in CC_AArch64_Custom_Block()
94 RegList = HRegList; in CC_AArch64_Custom_Block()
96 RegList = SRegList; in CC_AArch64_Custom_Block()
98 RegList = DRegList; in CC_AArch64_Custom_Block()
100 RegList = QRegList; in CC_AArch64_Custom_Block()
120 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
146 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dreglist-riscv64.h15 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 const RegList kJSCallerSaved = {t0, t1, t2, a0, a1, a2, a3, a4, a5, a6, a7, t4};
25 const RegList kCalleeSaved = {fp, // fp/s0
58 const RegList kSafepointSavedRegisters = kJSCallerSaved | kCalleeSaved;
/third_party/node/deps/v8/src/codegen/x64/
H A Dreglist-x64.h15 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 constexpr RegList kJSCallerSaved = {
25 constexpr RegList kCallerSaved =
/third_party/node/deps/v8/src/codegen/s390/
H A Dreglist-s390.h14 using RegList = RegListBase<Register>;
16 ASSERT_TRIVIALLY_COPYABLE(RegList);
23 const RegList kJSCallerSaved = {r1, r2, // r2 a1
31 const RegList kCalleeSaved = {r6, // r6 (argument passing in CEntryStub)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFre in CC_X86_32_MCUInReg()
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/third_party/node/deps/v8/src/codegen/mips64/
H A Dreglist-mips64.h15 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 const RegList kJSCallerSaved = {v0, v1, a0, a1, a2, a3, a4,
26 const RegList kCalleeSaved = {s0, // s0
/third_party/node/deps/v8/src/codegen/mips/
H A Dreglist-mips.h15 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 const RegList kJSCallerSaved = {v0, v1, a0, a1, a2, a3, t0,
26 const RegList kCalleeSaved = {s0, // s0
/third_party/node/deps/v8/src/codegen/loong64/
H A Dreglist-loong64.h15 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 const RegList kJSCallerSaved = {a0, a1, a2, a3, a4, a5, a6, a7,
26 const RegList kCalleeSaved = {fp, // fp
H A Dmacro-assembler-loong64.h281 void MaybeSaveRegisters(RegList registers);
282 void MaybeRestoreRegisters(RegList registers);
308 void MultiPush(RegList regs);
309 void MultiPush(RegList regs1, RegList regs2);
310 void MultiPush(RegList regs1, RegList regs2, RegList regs3);
354 void MultiPop(RegList regs);
355 void MultiPop(RegList regs
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/third_party/node/deps/v8/src/codegen/ppc/
H A Dreglist-ppc.h14 using RegList = RegListBase<Register>;
17 ASSERT_TRIVIALLY_COPYABLE(RegList);
24 const RegList kJSCallerSaved = {r3, // a1
41 const RegList kCalleeSaved = {r14, r15, r16, r17, r18, r19, r20, r21, r22,
/third_party/node/deps/v8/src/codegen/ia32/
H A Dreglist-ia32.h14 using RegList = RegListBase<Register>;
16 ASSERT_TRIVIALLY_COPYABLE(RegList);
20 constexpr RegList kJSCallerSaved = {
/third_party/vixl/src/aarch64/
H A Doperands-aarch64.h53 constexpr CPURegList(CPURegister::RegisterType type, unsigned size, RegList list) in CPURegList()
90 RegList list = (static_cast<RegList>(1) << number_of_registers) - 1; in All()
93 list |= (static_cast<RegList>(1) << kSPRegInternalCode); in All()
188 constexpr RegList GetList() const { in GetList()
194 VIXL_DEPRECATED("GetList", RegList list() const) { return GetList(); }
196 void SetList(RegList new_list) { in SetList()
200 VIXL_DEPRECATED("SetList", void set_list(RegList new_list)) {
211 CPURegister PopLowestIndex(RegList mask = ~static_cast<RegList>(
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H A Doperands-aarch64.cc33 CPURegister CPURegList::PopLowestIndex(RegList mask) { in PopLowestIndex()
34 RegList list = list_ & mask; in PopLowestIndex()
37 VIXL_ASSERT(((static_cast<RegList>(1) << index) & list) != 0); in PopLowestIndex()
43 CPURegister CPURegList::PopHighestIndex(RegList mask) { in PopHighestIndex()
44 RegList list = list_ & mask; in PopHighestIndex()
48 VIXL_ASSERT(((static_cast<RegList>(1) << index) & list) != 0); in PopHighestIndex()
H A Dregisters-aarch64.h39 typedef uint64_t RegList; typedef
40 static const int kRegListSizeInBits = sizeof(RegList) * 8;
120 RegList GetBit() const { in GetBit()
123 return static_cast<RegList>(1) << code_; in GetBit()
985 RegList unique_regs = 0;
986 RegList unique_vregs = 0;
987 RegList unique_pregs = 0;
/third_party/node/deps/v8/src/codegen/arm64/
H A Dreglist-arm64.h16 using RegList = RegListBase<Register>;
18 ASSERT_TRIVIALLY_COPYABLE(RegList);
21 constexpr int kRegListSizeInBits = sizeof(RegList) * kBitsPerByte;
37 CPURegList(int size, RegList list) in CPURegList()
/third_party/node/deps/v8/src/codegen/
H A Dreglist.h35 static constexpr RegList kEmptyRegList = {};
38 static constexpr RegList kAllocatableGeneralRegisters = {
H A Dinterface-descriptors.cc22 RegList reglist; in InitializeRegisters()
147 RegList allocatable_regs = data->allocatable_registers(); in Verify()
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-regalloc.h35 RegList free_registers_ = kAllocatableGeneralRegisters;
37 RegList used_registers() const { in used_registers()
61 RegList list = node->ClearRegisters(); in FreeRegisters()
/third_party/node/deps/v8/src/compiler/
H A Dlinkage.h39 constexpr RegList kNoCalleeSaved;
256 RegList callee_saved_registers, in CallDescriptor()
263 const RegList allocatable_registers = {}, in CallDescriptor()
415 RegList CalleeSavedRegisters() const { return callee_saved_registers_; } in CalleeSavedRegisters()
446 RegList AllocatableRegisters() const { return allocatable_registers_; } in AllocatableRegisters()
466 const RegList callee_saved_registers_;
470 const RegList allocatable_registers_;
/third_party/vixl/test/aarch64/
H A Dtest-utils-aarch64.h488 // The return value is a RegList indicating which registers were allocated.
489 RegList PopulateRegisterArray(Register* w,
494 RegList allowed);
497 RegList PopulateVRegisterArray(VRegister* s,
502 RegList allowed);
513 RegList reg_list,
518 RegList reg_list,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMELFStreamer.cpp85 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
159 assert(RegList.size() && "RegList should not be empty");
165 InstPrinter.printRegName(OS, RegList[0]);
167 for (unsigned i = 1, e = RegList.size(); i != e; ++i) {
169 InstPrinter.printRegName(OS, RegList[i]);
397 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
467 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
749 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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