Home
last modified time | relevance | path

Searched refs:RegClass (Results 1 - 25 of 86) sorted by relevance

1234

/third_party/mesa3d/src/amd/compiler/
H A Daco_ir.h308 struct RegClass { struct
338 RegClass() = default;
339 constexpr RegClass(RC rc_) : rc(rc_) {} in RegClass() function
340 constexpr RegClass(RegType type, unsigned size) in RegClass() function
354 constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); } in as_linear()
355 constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); } in as_subdword()
357 static constexpr RegClass get(RegType type, unsigned bytes) in get()
360 return RegClass(typ in get()
[all...]
H A Daco_reindex_ssa.cpp33 std::vector<RegClass> temp_rc = {s1};
44 RegClass rc = def.regClass(); in reindex_defs()
H A Daco_instruction_selection_setup.cpp240 RegClass
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
246 return RegClass::get(type, components * bitsize / 8u); in get_reg_class()
466 RegClass* regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id; in init_context()
585 RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components, in init_context()
593 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
745 RegClass rc = get_reg_class(ctx, type, intrinsic->dest.ssa.num_components, in init_context()
758 RegClass rc = in init_context()
772 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
792 RegClass r in init_context()
[all...]
H A Daco_register_allocation.cpp41 unsigned idx, RegClass rc);
43 RegClass rc);
45 get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr, RegClass rc);
50 RegClass rc;
60 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {} in assignment()
176 get_stride(RegClass rc) in get_stride()
206 RegClass rc;
208 DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc_, int operand) : rc(rc_) in DefInfo()
222 rc = RegClass::get(rc.type(), info.second); in DefInfo()
287 void block(PhysReg start, RegClass r
[all...]
H A Daco_reduce_assign.cpp60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
H A Daco_instruction_selection.h52 std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1)); in shader_io_state()
H A Daco_lower_to_hw_instr.cpp304 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1; in emit_int64_op()
391 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
431 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
1004 RegClass op_cls = src.op.regClass().resize(bytes); in split_copy()
1247 Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
1249 Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes())); in do_copy()
1620 RegClass r in handle_operands()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp33 const TargetRegisterClass &RegClass) { in constrainRegToClass()
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
35 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass()
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
88 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
91 if (!RegClass) { in constrainOperandRegClass()
30 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass) constrainRegToClass() argument
40 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx) constrainOperandRegClass() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
232 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
610 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
611 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
614 TII->get(getTeeOpcode(RegClass)), TeeRe in moveAndTeeForMultiUse()
[all...]
H A DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
120 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceTypes.h31 /// RegClass indicates the physical register class that a Variable may be
36 enum RegClass : uint8_t {
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-register.h22 enum RegClass : uint8_t {
56 static inline constexpr RegClass reg_class_for(ValueKind kind) { in reg_class_for()
86 // The table below illustrates how each RegClass is encoded, with brackets
90 // | RegClass | Example |
174 static LiftoffRegister from_code(RegClass rc, int code) { in from_code()
187 static LiftoffRegister from_external_code(RegClass rc, ValueKind kind, in from_external_code()
289 constexpr RegClass reg_class() const { in reg_class()
512 static constexpr LiftoffRegList GetCacheRegList(RegClass rc) { in GetCacheRegList()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; member in llvm::RegisterClassInfo
74 const RCInfo &RCI = RegClass[RC->getID()]; in get()
H A DRegisterScavenging.h166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, in scavengeRegister() argument
168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill); in scavengeRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h48 const TargetRegisterClass &RegClass);
51 /// TargetRegisterClass passed as an argument (RegClass).
63 const TargetRegisterClass &RegClass,
70 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
71 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
92 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
160 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
162 "Virtual register RegClass must be allocatable."); in createVirtualRegister()
166 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
H A DTargetInstrInfo.cpp52 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
54 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
57 if (RegClass < 0) in getRegClass()
61 return TRI->getRegClass(RegClass); in getRegClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp483 const TargetRegisterClass *RegClass =
664 RegClass->contains(FrameReg))) {
668 if (!MRI->constrainRegClass(FrameReg, RegClass))
705 RegClass->contains(FrameReg));
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
1935 Register TrueBBReg = MRI->createVirtualRegister(RegClass);
1936 Register FalseBBReg = MRI->createVirtualRegister(RegClass);
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2002 Register NextDestReg = MRI->createVirtualRegister(RegClass);
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2062 Register PHIDestReg = MRI->createVirtualRegister(RegClass);
2063 Register IfSourceReg = MRI->createVirtualRegister(RegClass);
2176 const TargetRegisterClass *RegClass =
2178 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass);
[all...]
H A DSIInstrInfo.cpp763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
764 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
765 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
766 RegClass == &AMDGPU::SReg_32_XM0RegClass || in materializeImmediate()
767 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) { in materializeImmediate()
773 if (RegClass == &AMDGPU::SReg_64RegClass || in materializeImmediate()
774 RegClass == &AMDGPU::SGPR_64RegClass || in materializeImmediate()
775 RegClass == &AMDGPU::SReg_64_XEXECRegClass) { in materializeImmediate()
781 if (RegClass == &AMDGPU::VGPR_32RegClass) { in materializeImmediate()
786 if (RegClass in materializeImmediate()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp706 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
708 RegClass = &AArch64::ZPRRegClass; in PrintAsmOperand()
710 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
712 RegClass = &AArch64::FPR128RegClass; in PrintAsmOperand()
717 return printAsmRegInClass(MO, RegClass, AltName, O); in PrintAsmOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; in convertMIMGInst()

Completed in 33 milliseconds

1234