| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 207 __ Rbit(PickR(size), PickR(size)); in GenerateTrivialSequence()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-macro-assembler-cond-rd-rn-a32.cc | 57 M(Rbit) \
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| H A D | test-macro-assembler-cond-rd-rn-t32.cc | 57 M(Rbit) \
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| H A D | test-simulator-cond-rd-rn-a32.cc | 117 M(Rbit) \
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| H A D | test-simulator-cond-rd-rn-t32.cc | 117 M(Rbit) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 295 V(rbit, Rbit) \
1080 inline void Rbit(const Register& rd, const Register& rn);
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| H A D | macro-assembler-arm64-inl.h | 846 void TurboAssembler::Rbit(const Register& rd, const Register& rn) { in Rbit() function in v8::internal::TurboAssembler
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 410 Rbit, enumerator
1055 using InstARM32Rbit = InstARM32UnaryopGPR<InstARM32::Rbit, false>;
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| H A D | IceInstARM32.cpp | 3450 template class InstARM32UnaryopGPR<InstARM32::Rbit, false>;
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1168 Rbit(dst.W(), src.W()); in emit_i32_ctz()
1182 Rbit(dst.gp().X(), src.gp().X()); in emit_i64_ctz()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1550 __ Rbit(i.OutputRegister64(), i.InputRegister64(0)); in AssembleArchInstruction()
1553 __ Rbit(i.OutputRegister32(), i.InputRegister32(0)); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2296 void Rbit(const Register& rd, const Register& rn) { in Rbit() function in vixl::aarch64::MacroAssembler
3045 V(rbit, Rbit) \
5735 void Rbit(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Rbit() function in vixl::aarch64::MacroAssembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-sve-aarch64.cc | 13597 __ Rbit(z0.VnB(), p1.Merging(), z0.VnB());
13598 __ Rbit(z0.VnB(), p1.Merging(), z0.VnB());
13600 __ Rbit(z1.VnB(), p1.Merging(), z0.VnB());
13601 __ Rbit(z2.VnH(), p1.Merging(), z0.VnH());
13602 __ Rbit(z3.VnS(), p1.Merging(), z0.VnS());
13603 __ Rbit(z4.VnD(), p1.Merging(), z0.VnD());
13606 __ Rbit(z5.VnB(), p2.Merging(), z0.VnB());
13608 __ Rbit(z6.VnS(), p2.Merging(), z0.VnS());
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| H A D | test-disasm-neon-aarch64.cc | 3572 COMPARE_MACRO(Rbit(v1.V8B(), v8.V8B()), in TEST()
3575 COMPARE_MACRO(Rbit(v2.V16B(), v9.V16B()), in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 5659 COMPARE_MACRO(Rbit(z22.VnB(), p2.Merging(), z24.VnB()), in TEST()
5661 COMPARE_MACRO(Rbit(z22.VnH(), p2.Merging(), z24.VnH()), in TEST()
5663 COMPARE_MACRO(Rbit(z22.VnS(), p2.Merging(), z24.VnS()), in TEST()
5665 COMPARE_MACRO(Rbit(z22.VnD(), p2.Merging(), z24.VnD()), in TEST()
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| H A D | test-assembler-aarch64.cc | 1503 __ Rbit(w0, w24); in TEST()
1504 __ Rbit(x1, x24); in TEST()
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| H A D | test-assembler-neon-aarch64.cc | 6955 __ Rbit(v28.V8B(), v1.V8B()); in TEST()
6956 __ Rbit(v29.V16B(), v1.V16B()); in TEST()
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3618 void Rbit(Condition cond, Register rd, Register rm) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3631 void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); } in MacroAssembler() function in vixl::aarch32::MacroAssembler
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