| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 89 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
90 return RSI.Instr == Instr; in operator ==()
110 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
112 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
117 void trackRSI(const RegSeqInfo &RSI);
198 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector()
200 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
201 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
208 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
209 E = RSI in RebuildVector()
197 RebuildVector( RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const RebuildVector() argument
291 tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, std::vector<std::pair<unsigned, unsigned>> &RemapChan) tryMergeUsingCommonSlot() argument
311 tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, std::vector<std::pair<unsigned, unsigned>> &RemapChan) tryMergeUsingFreeSlot() argument
324 trackRSI(const RegSeqInfo &RSI) trackRSI() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/marl/src/ |
| H A D | osfiber_asm_x64.h | 47 uintptr_t RSI; member
70 static_assert(offsetof(marl_fiber_context, RSI) == MARL_REG_RSI,
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| H A D | osfiber_x64.c | 37 ctx->RSI = (uintptr_t)arg; in marl_fiber_set_target()
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| /third_party/libunwind/libunwind/src/x86_64/ |
| H A D | init.h | 53 c->dwarf.loc[RSI] = REG_INIT_LOC(c, rsi, RSI); in common_init()
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| H A D | unwind_i.h | 43 #define RSI 4 macro
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| H A D | Gregs.c | 111 case UNW_X86_64_RSI: loc = c->dwarf.loc[RSI]; break; in tdep_access_reg()
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| H A D | Gos-solaris.c | 76 c->dwarf.loc[RSI] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSI, 0); in x86_64_handle_signal_frame()
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| H A D | Gos-freebsd.c | 115 c->dwarf.loc[RSI] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSI, 0); in x86_64_handle_signal_frame()
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| /third_party/musl/arch/x32/bits/ |
| H A D | reg.h | 16 #define RSI 13 macro
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| /third_party/musl/arch/x86_64/bits/ |
| H A D | reg.h | 16 #define RSI 13 macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 160 {codeview::RegisterId::RSI, X86::RSI}, in initLLVMToSEHAndCVRegMapping()
607 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
635 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
672 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
708 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
744 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
745 return X86::RSI; in getX86SubSuperRegisterOrZero()
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| /third_party/node/deps/v8/src/trap-handler/ |
| H A D | handler-inside-posix.cc | 143 auto* simulated_ip_reg = CONTEXT_REG(rsi, RSI); in TryHandleSignal()
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| /third_party/rust/crates/libc/src/fuchsia/ |
| H A D | x86_64.rs | 134 pub const RSI: ::c_int = 13; consts
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 179 ENTRY(RSI) \
197 ENTRY(RSI) \
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| H A D | X86Disassembler.cpp | 1823 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI; in translateSrcIndex()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86SelectionDAGInfo.cpp | 192 const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI; in emitRepmovs()
302 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
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| H A D | X86MCInstLower.cpp | 1455 const Register DestRegs[] = {X86::RDI, X86::RSI}; in LowerPATCHABLE_EVENT_CALL()
1552 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX}; in LowerPATCHABLE_TYPED_EVENT_CALL()
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| /third_party/lzma/Asm/x86/ |
| H A D | 7zAsm.asm | 135 r6 equ RSI
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| H A D | LoopUnswitch.cpp | 623 SelectInst *RSI = dyn_cast<SelectInst>(RHS); in EqualityPropUnSafe() local
624 if ((LSI && hasUndefInSelect(*LSI)) || (RSI && hasUndefInSelect(*RSI))) in EqualityPropUnSafe()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 375 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI || in isSrcIdx()
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| H A D | X86AsmParser.cpp | 1264 unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI); in DefaultMemSIOperand()
1283 case X86::RSI: in IsSIReg()
1299 return IsSIReg ? X86::RSI : X86::RDI; in GetSIDIForRegClass()
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| /third_party/libunwind/libunwind/src/ptrace/ |
| H A D | _UPT_reg_offset.c | 344 UNW_R_OFF(RSI, rsi)
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| /third_party/rust/crates/libc/src/unix/linux_like/android/b64/x86_64/ |
| H A D | mod.rs | 749 pub const RSI: ::c_int = 13; consts
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| /third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b64/x86_64/ |
| H A D | mod.rs | 764 pub const RSI: ::c_int = 13; consts
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| /third_party/rust/crates/libc/src/unix/linux_like/linux/musl/b64/x86_64/ |
| H A D | mod.rs | 626 pub const RSI: ::c_int = 13; consts
|